MCIMX27 Motorola Semiconductor Products, MCIMX27 Datasheet - Page 10

• Manufacturer Part Number: MCIMX27
• Manufacturer: Motorola Semiconductor Products

Functional Description and Application Information
2.3.3
The ARM926EJ-S Interrupt Controller (AITC) is a 32-bit peripheral that collects interrupt requests from
up to 64 sources and provides an interface to the ARM926EJ-S core. The AITC includes software
controlled priority levels for normal interrupts.
The AITC performs the following functions:
2.3.4
The ARM926EJ-S (ARM926) is a member of the ARM9 family of general-purpose microprocessors
targeted at multi-tasking applications. The ARM926 supports the 32-bit ARM and 16-bit Thumb
instructions sets. The ARM926 includes features for efficient execution of Java byte codes. A JTAG port
is provided to support the ARM Debug Architecture, along with associated signals to support the ETM9
real-time trace module. The ARM926EJ-S is a Harvard cached architecture including an ARM9EJ-S
integer core, a Memory Management Unit (MMU), separate instruction and data AMBA AHB interfaces,
separate instruction and data caches, and separate instruction and data tightly coupled memory (TCM)
interfaces. The ARM926 co-processor, instruction TCM, and data TCM interfaces will be tied off within
the ARM926 Platform and will not be available for external connection.
The ARM926EJ-S processor is a fully synthesizable macrocell, with a configurable memory system. Both
instruction and data caches will be 16 kbytes on the platform. The cache is virtually accessed and virtually
tagged. The data cached has physical tags as well. The MMU provides virtual memory facilities which are
required to support various platform operating systems such as Symbian OS, Windows CE, and Linux. The
MMU contains eight fully associative TLB entries for lockdown and 64 set associative entries. Refer to
the ARM926EJ-S Technical Reference Manual for more information.
2.3.5
The Advanced Technology Attachment (ATA) host controller complies with the ATA/ATAPI-6
specification. The primary use of the ATA host controller is to interface with IDE hard disc drives and
Advanced Technology Attachment Packet Interface (ATAPI) optical disc drives. It interfaces with the ATA
device over a number of ATA signals.
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Supports up to 64 interrupt sources
Supports fast and normal interrupts
Selects normal or fast interrupt request for any interrupt source
Indicates pending interrupt sources via a register for normal and fast interrupts
Indicates highest priority interrupt number via register. (Can be used as a table index.)
Independently can enable or disable any interrupt source
Provides a mechanism for software to schedule an interrupt
Supports up to 16 software controlled priority levels for normal interrupts and priority masking
Can single-bit disable all normal interrupts and all fast interrupts. (Used in enabling of secure
operations.)
ARM926EJ-S Interrupt Controller (AITC)
ARM926EJ-S Platform
Advanced Technology Attachment (ATA)
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Preliminary—Subject to Change Without Notice
Freescale Semiconductor