MCIMX27 Motorola Semiconductor Products, MCIMX27 Datasheet - Page 66

• Manufacturer Part Number: MCIMX27
• Manufacturer: Motorola Semiconductor Products

Signal Descriptions
3.5.13
Figure
signals of the NFC at module level, and
(NFC) timing parameters are based on the internal NFC clock generated by the Clock Controller module,
where time T is the period of the NFC clock in ns. The relationship between the NFC clock and the external
timing parameters of the NFC is provided in
Table 34
22.17 MHz and 33.25 MHz. Assuming a 266 MHz FCLK (CPU clock), NFCDIV should be set to
divide-by-12 to generate a 22.17 MHz NFC clock and divide-by-8 to generate a 33.25 MHz NFC clock.
The user should compare the parameters of the selected NAND Flash memory with the NFC external
timing parameters to determine the proper NFC clock. The maximum NFC clock allowed is 66 MHz. It
should also be noted that the default NFC clock on power up is 16.63 MHz.
66
MSHC_DATA
30,
Signal
also provides two examples of external timing parameters with NFC clock frequencies of
Figure
NAND Flash Controller Interface (NFC)
31,
NFIO[7:0]
Figure
NFALE
NFWE
NFCLE
NFCE
Table 33. Parallel Interface Timing Parameters (continued)
Output delay time
Figure 30. Command Latch Cycle Timing Diagram
32, and
Parameter
Setup time
Hold time
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Preliminary—Subject to Change Without Notice
NF6
NF1
NF3
Figure 33
Table 34
Table
tDsu
tDh
tDd
show the relative timing requirements among different
NF8
NF5
lists the timing parameters. The NAND Flash Controller
34.
command
Symbol
NF4
NF9
NF2
NF7
Min
8
1
Standards
Max
Freescale Semiconductor
15
ns
ns
ns
Unit