MCIMX27 Motorola Semiconductor Products, MCIMX27 Datasheet - Page 89

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MCIMX27

Manufacturer Part Number
MCIMX27
Description
Manufacturer
Motorola Semiconductor Products
Datasheet

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All the timings for the SSI are given for a non-inverted serial clock polarity
(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the
polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS shown in the tables and in the figures.
DAM1_T_FS (bl)
DAM1_T_FS (wl)
SS22
SS23
SS24
SS25
SS26
SS28
SS30
SS32
SS34
SS35
SS36
SS40
SS41
DAM1_T_CLK
ID
DAM1_RXD
(Input)
(Input)
(Input)
(Input)
Table 48. SSI Receiver with External Clock Timing Parameters
Figure 51. SSI Receiver with External Clock Timing Diagram
(Tx/Rx) CK clock period
(Tx/Rx) CK clock high period
(Tx/Rx) CK clock rise time
(Tx/Rx) CK clock low period
(Tx/Rx) CK clock fall time
(Rx) CK high to FS (bl) high
(Rx) CK high to FS (bl) low
(Rx) CK high to FS (wl) high
(Rx) CK high to FS (wl) low
(Tx/Rx) External FS rise time
(Tx/Rx) External FS fall time
SRXD setup time before (Rx) CK low
SRXD hold time after (Rx) CK low
SS23
SS28
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Preliminary—Subject to Change Without Notice
Parameter
SS22
External Clock Operation
SS32
SS35
SS30
NOTE
SS40
SS26
SS25
–10.0
–10.0
81.4
36.0
36.0
10.0
10.0
10.0
Min
2.0
SS41
SS24
SS36
Max
15.0
15.0
6.0
6.0
6.0
6.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Signal Descriptions
SS34
89

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