MCIMX27 Motorola Semiconductor Products, MCIMX27 Datasheet - Page 19

• Manufacturer Part Number: MCIMX27
• Manufacturer: Motorola Semiconductor Products

(M0–M5) fully functional master ports and three (S0–S2) fully functional slave ports. The MAX is
uni-directional. All master and slave ports are AHB-Lite compliant.
The design of the crossbar switch enables concurrent transactions to proceed from any master port to any
slave port. That is, it is possible for all three slave ports to be active at the same time as a result of three
independent master requests. If a particular slave port is simultaneously requested by more than one master
port, arbitration logic exists inside the crossbar to allow the higher priority master port to be granted the
bus, while stalling the other requestor(s) until that transaction has completed. The slave port arbitration
schemes supported are fixed, programmable fixed, programmable default input port parking, and a round
robin arbitration scheme.
The Crossbar Switch also monitors the ccm_br input (clock control module bus request), which requests
a bus grant from all four slave ports. The priority of ccm_br is programmable and defaults to the highest
priority. Upon receiving bus grants for all four output ports, the ccm_bg output will assert. At this point,
the clock control and reset module (CRM) can turn off hclk and be assured there are no outstanding AHB
transactions in progress. Once the CRM is granted a port, no other master will receive a grant on that port
until the CRM bus request (ccm_br) negates.
2.3.23
The Memory Stick Host Controller (MSHC) is located between the AIPI and the Sony Memory Stick and
provides support for data transfers between the i.MX27 processor and the Memory Stick (MS). The MSHC
consists of two sub-modules; the MSHC gasket and the Sony Memory Stick Host Controller (SMSC). The
SMSC module, which is the actual memory stick host controller, is compatible with Sony Memory Stick
Ver 1.x and Memory Stick PRO. The gasket connects the AIPI IP bus to the SMSC interface to allow
communication and data transfers via the IP Bus.
The MSHC gasket uses a reduced IP Bus interface that supports the IP bus read/write transfers that include
a back-to-back read or write. DMA transfers also take place via the IP Bus interface.
A transfer can be initiated by the DMA or the host (through the AIPI) response to an MSHC DMA request
or interrupt. The SMSC has two DMA address modes—a single address mode and a dual address mode.
The MSHC is set to dual-address mode for transfers with the DMA. In dual-address mode, when the
MSHC requests a transfer with the DMA request (XDRQ), the DMA will initiate a transfer to the MSHC.
2.3.24
NAND Flash Controller (NFC) interfaces standard NAND Flash devices to the i.MX27 processor and
hides the complexities of accessing the NAND Flash. It provides a glueless interface to both 8-bit and
16-bit NAND Flash parts with page sizes of 512 Bytes or 2 Kbytes. Its addressing scheme enables it to
access flash devices of almost limitless capacity. The 2-Kbyte RAM buffer of the NAND Flash is used as
the boot RAM during a cold reset (if the i.MX27 device is configured for a boot to be carried out from the
Freescale Semiconductor
Memory Stick Host Controller (MSHC)
NAND Flash Controller (NFC)
Details regarding the operation of the MSHC module can be found
separately in Memory Stick/Memory Stick PRO Host Controller IP
Specification 1.3.
i.MX27 Data Sheet, Advance Information, Rev. 0.1
Preliminary—Subject to Change Without Notice
NOTE
Functional Description and Application Information
19