MT54V1MH18E Micron Semiconductor Products, Inc., MT54V1MH18E Datasheet - Page 14

• Manufacturer Part Number: MT54V1MH18E
• Description: 18Mb QDR SRAM, 2.5V Vdd, Hstl, 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Notes
18Mb: 2.5V V
MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03
1. Outputs
2. Outputs are impedance-controlled. I
3. All voltages referenced to Vss (GND).
4. Overshoot: VIH(
5. AC load current is higher than the shown DC val-
6. HSTL outputs meet JEDEC HSTL Class I and Class
7. The nominal value of V
8. To maintain a valid level, the transitioning edge of
9. I
(V
2)/(RQ/5) for values of 175 W £ RQ £ 350 W .
Undershoot: VIL(
Power-up:
and V
During normal operation, V
V
pulse widths less than
cycle rates less than
ues. AC I/O curves are available upon request.
II standards.
range of 1.5V to 1.8V DC, and the variation of
V
the input must:
a. Sustain a constant slew rate from the current AC
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
increases with faster cycle times. I
with faster cycle times and greater output loading.
Typical value is measured at 6ns cycle time.
DD
DD
DD
V
maintain at least the target DC level, V
V
DD
DD
level through the target AC level, V
IH
IH
, HSTL, QDRb4 SRAM
. R#, W#, and address signals may not have
Q must be limited to ±0.1V DC.
is specified with no output current and
Q/2)/(RQ/5) for values of 175 W £ RQ £ 350 W .
(
(
DD
AC
DC
Q £ 1.4V for t £ 200ms
).
).
are
VIH £ V
impedance-controlled.
AC
AC
) ³ -0.5V for t £
) £ V
t
KHKH (MIN).
DD
t
DD
KHKL (MIN) or operate at
Q + 0.3V and V
DD
Q may be set within the
+ 0.7V for t £
DD
Q must not exceed
t
KHKH/2
DD
OL
DD
= (V
t
increases
KHKH/2
IL
IL
|I
(
OH
(
AC
£ 2.4V
DC
DD
|
) or
) or
Q/
=
14
10. Typical values are measured at V
11. NOP currents are valid when entering NOP after
12. Average I/O current and power is provided for
13. This parameter is sampled.
14. Average thermal resistance between the die and
15. Junction temperature is a function of total device
16. This is a synchronous device. All addresses, data,
17. Test conditons specified with the output loading,
18. Control input signals may not be operated with
19. If C and C# are tied HIGH, then K and K# become
20.
1.5V, and temperature = 25°C.
all pending READ and WRITE cycles are com-
pleted.
informational purposes only and is not tested.
Calculation assumes that all outputs are loaded
with C
of outputs toggle at each transition (n = 18 for the
x36), C
tions: Average I/O Power as dissipated by the
SRAM is: P = 0.5 × n × f × V
Average IDDQ = n × f × V
the case top surface per MIL SPEC 883 Method
1012.1.
power dissipation and device mounting environ-
ment. Measured per SEMI G38-87.8.
and control lines must meet the specified setup
and hold times for all latching clock edges.
as shown in Figure 5 unless otherwise noted.
pulse widths less than
the references for C and C# timing parameters.
t
age and temperature.
2.5V V
CHQX1 is greater than
Micron Technology, Inc., reserves the right to change products or specifications without notice.
L
O
(in farads), f = input clock frequency, half
= 6pF, V
DD
1 MEG x 18, 512K x 36
, HSTL, QDRb4 SRAM
DD
Q = 1.5V and uses the equa-
t
KHKL (MIN).
t
DD
CHQZ at any given volt-
DD
Q x (C
Q
2
x (C
DD
L
©2003 Micron Technology, Inc.
+ C
L
=2.5V, V
+ 2C
O
).
O
).
DD
Q =