MT54V1MH18E Micron Semiconductor Products, Inc., MT54V1MH18E Datasheet - Page 8

• Manufacturer Part Number: MT54V1MH18E
• Description: 18Mb QDR SRAM, 2.5V Vdd, Hstl, 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

Table 4:
18Mb: 2.5V V
MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03
SYMBOL
CQ#, CQ Output Synchronous Echo Clock Outputs: The edges of these outputs are tightly matched to the synchronous
BW_#
V
TMS
TDO
V
TCK
V
TDI
W#
V
ZQ
NC
D_
K#
SA
Q_
DD
C#
R#
REF
C
K
DD
SS
Q
DD
, HSTL, QDRb4 SRAM
Output Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K#
Output IEEE 1149.1 Test Output: 2.5V I/0 level.
Supply Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions for range.
Supply Power Supply: Isolated Output Buffer Supply. Nominally, 1.5V. 1.8V is also permissible. See DC Electrical
Supply Power Supply: GND.
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
–
Ball Descriptions
Synchronous Byte Writes: When LOW, these inputs cause their respective bytes to be registered and
written if W# had initiated a WRITE cycle. These signals must meet setup and hold times around the
rising edges of K and K# for each of the four rising edges comprising the WRITE cycle. See Ball Layout
figures for signal to data relationships.
Output Clock: This clock pair provides a user-controlled means of tuning device output data. The rising
edge of C# is used as the output timing reference for first output data. The rising edge of C is used as
the output reference for second output data. Ideally, C# is 180 degrees out of phase with C. C and C#
may be tied HIGH to force the use of K and K# as the output reference clocks instead of having to
provide C and C# clocks. If tied HIGH, these inputs may not be allowed to toggle during device
operation.
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and
K# during WRITE operations. See Ball Layout figures for ball site location of individual signals. The x18
device uses D0:D17, and the x36 device uses D0:D35.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase
with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
Synchronous Read: When LOW, this input causes the address inputs to be registered and a READ cycle
to be initiated. This input must meet setup and hold times around the rising edge of K and is ignored
on the subsequent rising edge of K.
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. See Ball Layout figures for address expansion inputs. All transactions
operate on a burst of four words (two clock periods of bus activity). These inputs are ignored when
both ports are deselected.
IEEE 1149.1 Clock Input: 2.5V I/O levels. This ball must be tied to V
the circuit.
IEEE 1149.1 Test Inputs: 2.5V I/O levels. These balls may be left as No Connects if the JTAG function is
not used in the circuit.
HSTL Input Reference Voltage: Nominally V
margin. Provides a reference voltage for the HSTL input buffer trip point.
Synchronous Write: When LOW, this input causes the address inputs to be registered and a WRITE
cycle to be initiated. This input must meet setup and hold times around the rising edge of K and is
ignored on the subsequent rising edge of K. This input is also ignored if a READ cycle is being initiated.
Output Impedance Matching Input: This input is used to tune the device outputs to the system data
bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a resistor from this ball to
ground. Alternately, this ball can be connected directly to V
mode. This ball cannot be connected directly to GND or left unconnected.
data outputs and can be used as data valid indication. These signals run freely and do not stop when Q
tri-states.
rising edges if C and C# are tied HIGH. This bus operates in response to R# commands. See Ball Layout
figures for ball site location of individual signals. The x18 device uses Q0:Q17, and the x36 device uses
Q0:35.
Characteristics and Operating Conditions for range.
No Connect: These balls are internally connected to the die, but have no function and may be left not
connected to the board to minimize ball count.
8
DD
DESCRIPTION
Q/2, but may be adjusted to improve system noise
2.5V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
1 MEG x 18, 512K x 36
Q to enable the minimum impedance
, HSTL, QDRb4 SRAM
SS
if the JTAG function is not used in
©2003 Micron Technology, Inc.