MT55L128L32F1 Micron Semiconductor Products, Inc., MT55L128L32F1 Datasheet - Page 10

• Manufacturer Part Number: MT55L128L32F1
• Description: 4Mb ZBT SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

FBGA PIN DESCRIPTIONS (continued)
10L, 10M, 11D, 10L, 10M, 11J,
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
MT55L256L18F1_F.p65 – Rev. F, Pub. 1/03 EN
11E, 11F, 11G 11K, 11L, 11M
(a)
1L, 1M, 2D,
3K, 3L, 3M,
3N, 9C, 9D,
8G, 8H, 8J,
8K, 8L, 8M
3C, 3D, 3E,
4E, 4F, 4G,
4H, 4J, 4K,
8D, 8E, 8F,
9E, 9F, 9G,
3F, 3G, 3J,
9J, 9K, 9L,
(b)
2E, 2F, 2G
2H, 4D,
4L, 4M,
9M, 9N
10J, 10K,
x 1 8
11C
8A
1J, 1K,
1N
1R
–
–
10F, 10G, 11D,
11E, 11F, 11G
(d)
(b)
(a)
3K, 3L, 3M,
3N, 9C, 9D,
1F, 1G, 2D,
1M, 2J, 2K,
8G, 8H, 8J,
8K, 8L, 8M
3C, 3D, 3E,
4E, 4F, 4G,
4H, 4J, 4K,
8D, 8E, 8F,
9E, 9F, 9G,
3F, 3G, 3J,
9J, 9K, 9L,
2E, 2F, 2G
x32/x36
(c)
2H, 4D,
4L, 4M,
9M, 9N
2L, 2M
1J, 1K, 1L,
10D, 10E,
10J, 10K,
11N
11C
1D, 1E,
8A
1N
1R
1C
S Y M B O L T Y P E
ADV/LD# Input Synchronous Address Advance/Load: When HIGH, this input is
NC/DQPb
NC/DQPd
NC/DQPa
NC/DQPc
MODE
(LB0#)
V
DQb
DQd
DQa
DQc
V
DD
DD
Q
Output Byte “b” is associated with DQbs. For the x32 and x36 versions,
Supply Power Supply: See DC Electrical Characteristics and Operating
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQas;
Input
NC/
I/O
(continued on next page)
used to advance the internal burst counter, controlling burst
access after the external address is loaded. When ADV/LD# is
HIGH, R/W# is ingored. A LOW on ADV/LD# clocks a new
address at the CLK rising edge.
Mode: This input selects the burst sequence. A LOW on this input
selects “linear burst.” NC or HIGH on this input selects “interleaved
burst.” Do not alter input state while device is operating.
Byte “a” is associated with DQas; Byte “b” is associated with DQbs;
Byte “c” is associated with DQcs; Byte “d” is associated with DQds.
Input data must meet setup and hold times around the rising edge
of CLK.
No Connect/Parity Data I/Os: On the x32 version, these are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
Conditions for range.
Operating Conditions for range.
10
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D E S C R I P T I O N
©2003, Micron Technology, Inc.