MT55L128L32F1 Micron Semiconductor Products, Inc., MT55L128L32F1 Datasheet - Page 3

• Manufacturer Part Number: MT55L128L32F1
• Description: 4Mb ZBT SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

GENERAL DESCRIPTION (continued)
data inputs, chip enable (CE#), two additional chip
enables for easy depth expansion (CE2, CE2#), cycle
start input (ADV/LD#), synchronous clock enable
(CKE#), byte write enables (BWa#, BWb#, BWc#, and
BWd#) and read/write (R/W#).
(OE#, which may be tied LOW for control signal minimi-
zation), clock (CLK) and snooze enable (ZZ, which may
be tied LOW if unused). There is also a burst mode pin
(MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left
unconnected if burst is unused. The flow-through data-
out (Q) is enabled by OE#. WRITE cycles can be from
one to four bytes wide as controlled by the write control
inputs.
ated by the ADV/LD# input. Subsequent burst ad-
dresses can be internally generated as controlled by
the burst advance pin (ADV/LD#). Use of burst mode
is optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap
around after the fourth access from a base address.
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
MT55L256L18F1_F.p65 – Rev. F, Pub. 1/03 EN
Asynchronous inputs include the output enable
All READ, WRITE and DESELECT cycles are initi-
The synchronous inputs include all addresses, all
3
bus, the flow-through ZBT SRAM uses a LATE WRITE
cycle. For example, if a WRITE cycle begins in clock
cycle one, the address is present on rising edge one.
BYTE WRITEs need to be asserted on the same cycle as
the address. The write data associated with the ad-
dress is required one cycle later, or on the rising edge of
clock cycle two.
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa# con-
trols DQa pins; BWb# controls DQb pins; BWc# controls
DQc pins; and BWd# controls DQd pins. Cycle types
can only be defined when an address is loaded, i.e.,
when ADV/LD# is LOW. Parity/ECC bits are only avail-
able on the x18 and x36 versions.
power supply, and all inputs and outputs are LVTTL-
compatible. Users can choose either a 2.5V or 3.3V I/O
version. The device is ideally suited for systems requir-
ing high bandwidth and zero bus turnaround delays.
sramds) for the latest data sheet.
To allow for continuous, 100 percent use of the data
Address and write control are registered on-chip to
Micron’s 4Mb ZBT SRAMs operate from a +3.3V V
Please refer to Micron’s Web site
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(www.micron.com/
©2003, Micron Technology, Inc.
DD