MT57V256H36P Micron Semiconductor Products, Inc., MT57V256H36P Datasheet

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... All synchronous inputs pass through reg- isters controlled by an input clock pair (K and K#) and are 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 2. HSTL, PIPELINED DDR SRAM DD ...

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... CQ, CQ# do not tristate except during some JTAG test modes. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. are not required when switching from a WRITE to a READ READ occurs after a WRITE cycle, address and data for the WRITE are stored in registers ...

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... Return CLK# Source CLK 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD of the impedance is transparent to the system. Imped- ance updates do not affect device operation, and all data sheet timing and current specifications are met during an update ...

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... DQ34 DQ33 DQ35 R TDO TCK SA *Expansion addresses: 9A for 18Mb, 3A for 36Mb, 10A for 72Mb, 2A for 144Mb. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD BALL ASSIGNMENT (Top View) 165-Ball FBGA R/ ...

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... TCK 2H, 10H V REF 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD TYPE Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. Balls 9A, 3A, 10A, and 2A are reserved for the next higher-order address inputs on 18, 36, 72, and 144Mb devices, respectively ...

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... V , HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD TYPE Input/ Synchronous Data IOs: Input data must meet setup and hold Output times around the rising edges of K and K#. Output data is synchronized to the respective C and C# data clocks and and C# are tied to HIGH ...

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... NOTE: 1. SA0 and SA1 are internally advanced in accordance with the burst order table. Bus cycle is terminated after burst count = 4. 2. State transitions (LD# = LOW (LD# = HIGH (R/W# = HIGH (R/W# = LOW). 3. State machine control timing sequence is controlled by K. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD X...X01 X...X10 X...X10 X ...

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... It is recommended that /C# when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD LD# R/W# ...

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... Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, V 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. *Stresses greater than those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the de- vice ...

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... Average I/O current and power is provided for information purposes only and is not tested. Calculation assumes that all outputs are loaded with C equations: Average I/O Power as dissipated by the SRAM is 0.5 × n × f × C × 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. CONDITIONS KHKH (MIN) ...

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... Average thermal resistance between the die and the case top surface per MIL SPEC 883 Method 1012.1. 3. Junction temperature is a function of total device power dissipation and device mounting environment. Measured per SEMI G38-87. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD CONDITIONS SYMBOL ...

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... are tied HIGH become the references for C, C# timing parameters. 6. Transition is measured ±100mV from steady state voltage CHQXI is greater than CHQZ at any given voltage and temperature. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD V +2.6V) DD SYMBOL MIN t KHKH 5 ...

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... Input rise and fall times .................................... 0.7ns Input timing reference levels ........................... 0.75V Output reference levels ................................. V ZQ for 50 impedance ...................................... 250 Output load ........................................... See Figure 1 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD Output Load Equivalent Q/2 DD SRAM 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

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... Outputs are disabled (High-Z) one clock cycle after a NOP. 3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. READ/WRITE TIMING NOP NOP ...

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... NOTE:The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. TEST ACCESS PORT (TAP) TEST CLOCK (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK ...

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... TDI TCK TMS 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path ...

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... TDI and TDO balls and allows the IDCODE to be shifted out of the 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD device when the TAP controller enters the Shift-DR state. ...

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... CH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figure 4. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD RESERVED These instruction are not implemented but are re- served for future use ...

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... Undershoot: V (AC) -0.5V for t IL Power-up: V +2.6V and V IH During normal operation pulse widths less than KHKL (MIN) or operate at frequencies exceeding 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. 2.5V SS +2.6V unless otherwise noted) CONDITIONS SYMBOL ...

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... RESERVED 101 RESERVED 110 BYPASS 111 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. DESCRIPTION 000 Reserved for version number. Defines width of x36 bits. Reserved for future use. Allows unique identification of SRAM vendor. 1 Indicates the presence register. ...

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... DQ12 24 DQ13 25 DQ14 26 DQ15 27 DQ16 28 DQ17 GND/SA20 31 NC/SA18 SA1 34 SA0 35 LD# 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. Boundary Scan (Exit) Order Ball ID BIT 10P 46 11P ...

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... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc. 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD 165-BALL FBGA ...

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... Rev. 2, ADVANCE ..................................................................................................................................................... 9/01 • Changed AC Electrical Characteristics chart • Updated formats Original document, ADVANCE ................................................................................................................................ 3/00 256K HSTL, Pipelined DDR SRAM DD MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02 2. HSTL, PIPELINED DDR SRAM DD 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. 256K x 36 ...