MT57V256H36P Micron Semiconductor Products, Inc., MT57V256H36P Datasheet - Page 15

• Manufacturer Part Number: MT57V256H36P
• Description: 9Mb DDR SRAM 2.5V Vdd, HSTL Pipelined
• Manufacturer: Micron Semiconductor Products, Inc.

IEEE 1149.1 SERIAL BOUNDARY SCAN
(JTAG)
test access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the set
of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded be-
cause their inclusion places an added delay in the critical
speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the
operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC-standard 2.5V I/O
logic levels.
ister, boundary scan register, bypass register, and ID
register.
DISABLING THE JTAG FEATURE
JTAG feature. To disable the TAP controller, TCK must be
tied LOW (V
TMS are internally pulled up and may be unconnected.
They may alternately be connected to V
up resistor. TDO should be left unconnected. Upon
power-up, the device will come up in a reset state which
will not interfere with the operation of the device.
NOTE:The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
256K x 36 2.5V V
MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02
The DDR SRAM incorporates a serial boundary scan
The SRAM contains a TAP controller, instruction reg-
It is possible to operate the SRAM without using the
DD
, HSTL, Pipelined DDR SRAM
SS
) to prevent clocking of the device. TDI and
1
0
TEST-LOGIC
RUN-TEST/
RESET
IDLE
0
TAP Controller State Diagram
DD
through a pull-
1
1
0
Figure 2
2.5V V
CAPTURE-DR
UPDATE-DR
PAUSE-DR
EXIT1-DR
EXIT2-DR
DR-SCAN
SHIFT-DR
1
SELECT
0
0
1
0
1
1
15
0
TEST ACCESS PORT (TAP)
TEST CLOCK (TCK)
inputs are captured on the rising edge of TCK. All outputs
are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
controller and is sampled on the rising edge of TCK. It is
allowable to leave this ball unconnected if the TAP is not
used. The ball is pulled up internally, resulting in a logic
HIGH level.
TEST DATA-IN (TDI)
the registers and can be connected to the input of any of
the registers. The register between TDI and TDO is cho-
sen by the instruction that is loaded into the TAP instruc-
tion register. For information on loading the instruction
register, see Figure 2. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application.
TDI is connected to the most significant bit (MSB) of any
register. (See Figure 3.)
1
1
DD
0
0
The test clock is used only with the TAP controller. All
The TMS input is used to give commands to the TAP
The TDI ball is used to serially input information into
Micron Technology, Inc., reserves the right to change products or specifications without notice.
, HSTL, PIPELINED DDR SRAM
1
0
CAPTURE-IR
UPDATE-IR
PAUSE-IR
1
IR-SCAN
SHIFT-IR
EXIT1-IR
EXIT2-IR
SELECT
0
0
1
0
1
1
0
1
1
0
0
256K x 36
©2002, Micron Technology, Inc.