MT58L1MY18P Micron Semiconductor Products, Inc., MT58L1MY18P Datasheet - Page 25

• Manufacturer Part Number: MT58L1MY18P
• Description: 18Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O; 2.5V Vdd, 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

instruction register, the SRAM responds as if a SAM-
PLE/PRELOAD instruction has been loaded. There is
one difference between the two instructions. Unlike
the SAMPLE/PRELOAD instruction, EXTEST places
the SRAM outputs in a High-Z state.
IDCODE
32-bit code to be loaded into the instruction register. It
and TDO balls and allows the IDCODE to be shifted
out of the device when the TAP controller enters the
Shift-DR state.
tion register upon power-up or whenever the TAP con-
troller is given a test logic reset state.
SAMPLE Z
scan register to be connected between the TDI and
TDO balls when the TAP controller is in a Shift-DR
state. It also places all SRAM outputs into a High-Z
state.
SAMPLE/PRELOAD
tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bidirectional balls is captured in the boundary
scan register.
clock can only operate at a frequency up to 10 MHz,
while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in
18Mb: 1 Meg x 18, 512K x 32/36, Pipelined, SCD SyncBurst SRAM
MT58L1MY18P1_16_D.fm – Rev. D, Pub 2/03
When an EXTEST instruction is loaded into the
The IDCODE instruction causes a vendor-specific,
also places the instruction register between the TDI
The IDCODE instruction is loaded into the instruc-
The SAMPLE Z instruction causes the boundary
SAMPLE/PRELOAD is a 1149.1 mandatory instruc-
When the SAMPLE/PRELOAD instruction is loaded
The user must be aware that the TAP controller
25
PIPELINED, SCD SYNCBURST SRAM
the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not
harm the device, but there is no guarantee as to the
value that will be captured. Repeatable results may not
be possible.
capture the correct value of a signal, the SRAM signal
must be stabilized long enough to meet the TAP con-
troller’s capture setup plus hold time (
rectly if there is no way in a design to stop (or slow) the
clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals
and simply ignore the value of the CLK captured in the
boundary scan register.
the data by putting the TAP into the Shift-DR state.
This places the boundary scan register between the
TDI and TDO balls.
is not implemented, putting the TAP to the Update-DR
state while performing a SAMPLE/PRELOAD instruc-
tion will have the same effect as the Pause-DR com-
mand.
BYPASS
instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between the TDI
and TDO balls. The advantage of the BYPASS instruc-
tion is that it shortens the boundary scan path when
multiple devices are connected together on a board.
Reserved
reserved for future use. Do not use these instructions.
18Mb: 1 MEG x 18, 512K x 32/36
To guarantee that the boundary scan register will
The SRAM clock input might not be captured cor-
Once the data is captured, it is possible to shift out
Note that since the PRELOAD part of the command
When the BYPASS instruction is loaded in the
These instructions are not implemented but are
Micron Technology, Inc., reserves the right to change products or specifications without notice.
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©2003 Micron Technology, Inc.
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