MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 116
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MT90222AG
Manufacturer Part Number
MT90222AG
Description
Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90222AG.pdf
(155 pages)
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Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:12
Bit #
Bit #
Bit #
15:0
11:0
1. Bit is present only for Link 0. In all other Link Status Registers, this bit is set to 0.
2. Bit is present only for Link 0. In all other Link Status Registers, this bit is set to 0.
4
3
2
1
0
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R
R
R
Unused. Read all 0’s.
Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in
the IRQ Link Status register is set.
Each bit represents a link. A ’1’ means that the corresponding link has a valid request for
interrupt. The level of the IRQ pin is controlled by the bits in this register and the
corresponding bits in the IRQ Master Enable Register. A write does not have any affect on
the bits in this register. The status bit is not latched and changing the mask bit in the IRQ
Master Register has a direct effect on the level of the IRQ pin.
IV. The Link has received an ICP cell which contain a violation as defined in Table 16 of
IMA Spec. This status bit can be cleared by writing a ’0’ to it.
LODS. The Link is Out of Delay Synchronization. This status bit can be cleared by writing
a ’0’ to it.
LIF. Loss of IMA Frame. This status bit can be cleared by writing a ’0’ to it.
LCD Loss of Cell Delineation. This status bit can be cleared by writing a ’0’ to it.
Link Counter Overflow Interrupt. One or more counters associated with the link
overflowed. This status bit can be cleared only by reading or writing to the counter(s)
which is (are) the source for the IRQ.
0x0445 - 0x0454 (16 reg)
1 Enable register per link Status reg
0000
0x0455 (1 reg)
1 register for all 16 links
0000
0x0435 - 0x0444 (16 reg)
1 Status register per link
0000
Table 95 - IRQ Link Status Registers (continued)
Table 97 - IRQ Master Status Register
Table 96 - IRQ Link Enable Registers
Zarlink Semiconductor Inc.
MT90222/3/4
116
Description
Description
Description
Data Sheet
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