MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 121
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MT90222AG
Manufacturer Part Number
MT90222AG
Description
Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90222AG.pdf
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Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:12
Bit #
Bit #
Bit #
15:5
4:0
11
10
15
14
...
9
1
0
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
Unused. Read 0’s.
Reserved. Write 0 for normal operation.
Automatic ATM cell synchronization
When 1: automatic ATM cell synchronization enabled. To be used when no RXSYNC
signal is provided. Register 0x0741 must also be initialized.
When 0: automatic ATM cell synchronization disabled.
Reserved. Write 0 for normal operation.
TXSYNC Sync signal faulty on link 15. Cleared by writing ’0’.
TXSYNC Sync signal faulty on link 14. Cleared by writing ’0’.
....
TXSYNC Sync signal faulty on link 1. Cleared by writing ’0’.
TXSYNC Sync signal faulty on link 0. Cleared by writing ’0’.
Unused. Read all 0’s.
These 5 bits are used to select the source for the signal at PLLREF0:
The valid combinations are:
00000: RXCK0 01000: RXCK8
00001: RXCK1 01001: RXCK9
00010: RXCK2 01010: RXCK10 10010: RXSYNC2 11010: RXSYNC10
00011: RXCK3 01011: RXCK11 10011: RXSYNC3 11011: RXSYNC11
00100: RXCK4 01100: RXCK12 10100: RXSYNC4 11100: RXSYNC12
00101: RXCK5 01101: RXCK13 10101: RXSYNC5 11101: RXSYNC13
00110: RXCK6 01110: RXCK14 10110: RXSYNC6 11110: RXSYNC14
00111: RXCK7 01111: RXCK15 10111: RXSYNC7 11111: RXSYNC15
0x0700 - 0x070F (16 reg)
1 reg. per RX link
0000
0x0633 (1 reg)
1 reg. for all 16 RX links
0000
0x0634- 0x0635 (2 reg)
0000
Table 107 - PLL Reference Control Register
Table 108 - TDM RX Link Control Register
Table 106 - TX Sync. Status Register
Zarlink Semiconductor Inc.
MT90222/3/4
121
10000: RXSYNC0 11000: RXSYNC8
10001: RXSYNC1 11001: RXSYNC9
Description
Description
Description
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