MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 62

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

4.8.4
The MT90222/3/4 implements circuitry to determine whether or not a selected clock signal is active. This feature is
used to ensure a clock is operational before using it as a source for one or more transmit links. A read of the TXCK
Status (0x0630), RXCK Status (0x0631) or REFCK Status (0x0632) register indicates a faulty clock if a bit is ’1’.
A value of ’0’ for these bits means that activity was observed on this clock. This circuitry does not measure the
frequency of a clock signal, it only detects activity on the TXCK, RXCK and REFCK signals.
4.8.5
The clock selection circuitry selects the desired clock signal and ensures a smooth, glitch free, transition between
the current clock source and the new clock source. Clock source activity can be verified using the TXCK Status
(0x0630), RXCK Status (0x0631) or REFCK Status (0x0632) registers.
5.0
The MT90222/3/4 supports the UTOPIA L1 and L2 Mode, 8 or 16 bit wide bus at up to 52MHz, with odd/even parity,
for cell level handshake only. Each port can be assigned an address ranging from 0 to 30. The address value of 31
is reserved and should not be used.
The TX and RX paths of each IMA Group and each link in TC has its own PHY address. These PHY addresses are
defined in the UTOPIA Input Link Address (0x0040-0x0047) registers, UTOPIA Input Group Address
(0x0048-0x004B) registers, UTOPIA Output Link Address (0x000-0x0007) registers, and the UTOPIA Output
Group Address (0x0008-0x000B) registers. The UTOPIA Input LINK PHY Enable (0x0050) and the UTOPIA
Output Link PHY Enable (0x0010) registers are used to enable the PHY Address of the links in TC mode. The
UTOPIA Input Group PHY Enable (0x0051) register and the UTOPIA Output Group PHY Enable (0x0011)
registers are used to enable the PHY Address of the IMA Groups.
The MT90222/3/4 UTOPIA port uses handshaking signals to process data streams. The start of a cell (SOC) is
marked by the UTOPIA SOC sync signal. This signal is active during the transfer of the first byte/first word of a cell.
The 52 bytes/26 words that follow the arrival of the first byte/first word of a cell are interpreted as belonging to the
same cell and are stored accordingly (note that SOC sync signals received during the loading of these 52 bytes/26
words are ignored).
The Cell Available status line (Clav) is used to communicate to the ATM controller whether the MT90222/3/4 has
space for a cell in the PHY address that was polled in the previous cycle. Whenever there is space for a cell in the
TX direction or a cell ready in the RX direction, the TXClav and/or RXClav signal will be driven High or Low. When
the address does not correspond to any enabled PHY address inside the MT90222/3/4, the TXClav and RXClav
signal are set to High impedance mode. The use of an external pull-down may be required for the proper operation
of the Utopia bus in MPHY mode.
Note that the transmit or receive Utopia clock frequencies do not have to be synchronized with the system clock but
their frequencies cannot exceed the system clock frequency.
5.1
The UTOPIA interface input clock TxClk is independent of the system clock. The UTOPIA TxClk can be up to 52
MHz. The incoming cell is stored directly in the internal TX Cell RAM where the TX UTOPIA FIFOs are
implemented.
The TX byte clock (TxClk) is checked against the system clock. If the incoming byte clock frequency is lower than
1/128 of the system clock, bit 2 of the General Status (0x040E) register will be set. This bit is cleared by
overwriting it with 0. This aids in debugging as the presence of a UTOPIA clock is required not only for data
transfer but also for proper operation of the UTOPIA registers.
ATM Input Port
UTOPIA Interface Operation
Verification of Clock Activity
Clock Selection
Zarlink Semiconductor Inc.
MT90222/3/4
62
Data Sheet