MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 45
MT90222AG
Manufacturer Part Number
MT90222AG
Description
Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90222AG.pdf
(155 pages)
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3.2
The block diagram at Figure 9 illustrates the MT90224 IMA mode receive path. The receiver must rearrange the
incoming bit streams from up to 16 links into a single UTOPIA cell stream.
3.2.1
In IMA mode, the transmitter inserts special ICP cells in the various outgoing streams every M ATM cells to comply
with the IMA specification. The receive block uses these ICP cells to synchronize with the Far End transmit side and
to reconstruct the original ATM cell sequence.
3.2.2
The MT90222/3/4 implements IMA Frame Synchronization State Machines (IFSM) for each link, as described in
Section 11 of the IMA Specification. The values of Alpha, Beta and Gamma are programmable through the IMA
Frame Delineation (0x00CA) register. Their values are the same for all links.
After the link is programmed to be in IMA mode by writing to the RX Link Control (0x00C0-0x00C7) register, the
IMA Frame State Machine is enabled. At the same time, the parameter’s values of the RX link are latched in internal
reference registers and are used to determine whether the received ICP cell meets the valid ICP cell criteria to
determine IMA frame synchronization.
RXSYNC
RXSYNC
RXCK
RXCK
DSTi
DSTi
ATM Receive Path in IMA Mode
[15]
[0]
ICP Cell Processor
IMA Frame Synchronization
To TDM Ring
S/P
S/P
TDM Ring
Control
Figure 9 - MT90224 Receiver Circuit in IMA Mode
Registers
Link Info
Delin.
Delin.
Cell
Cell
TX Block
From
Zarlink Semiconductor Inc.
MT90222/3/4
Proc.
Proc.
ICP
ICP
45
Micro
RX Cell
Buffer
Machine
Machine
Frame
Frame
State
State
IMA
IMA
RAM Area
Controller
Recovery
RAM
Rate
Recovered
Scheduler
Cell CLK
RX
Data Sheet
UTOPIA
Interface
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