MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 123

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Reset Value (Hex):
Address
Address (Hex):
Direct access
Reset Value (Hex):
Direct access
Bit #
Bit #
Bit #
15:8
Offset
15:0
(Hex)
7:0
15
14
...
1
0
00
20
40
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
R/W
R/W
R/W
R
RXSYNC signal faulty on link 15. Cleared by writing ’0’.
RXSYNC signal faulty on link 14. Cleared by writing ’0’.
....
RXSYNC signal faulty on link 1. Cleared by writing ’0’.
RXSYNC signal faulty on link 0. Cleared by writing ’0’.
Unused. Read 0’s.
Must write with 54 (0x36) in Bit mode cell delineation. Not used in Byte mode cell
delineation.
Old ICP cell, Link 0.
New ICP cell, Link 0.
Old ICP cell, Link 1.
Each bit controls if the corresponding time slot is used to carry ATM Traffic. When not in
use, the DSTi pin is ignored for the corresponding time slot
This registers controls time slots 31:16. For T1 links, bit 8 (timeslot 24) must be zero.
0x0800 - 0x0BFF, 32 Blocks of 32 words (16 bit wide)
Access these locations directly, then use the transfer command
unknown
0x0730 (1 reg)
1 reg. for all 16 RX links
0000
0x0741 (1 reg)
1 reg. for all RX links
0000
Table 112 - RX Automatic ATM Synchronization Register
0x0720 - 0x072F (16 reg)
Control time slot 31:16
0000
to copy to internal memory
Table 110 - TDM RX Mapping (timeslots 31:16) Register
Table 111 - RX Sync. Status Register
Table 113 - RX IMA ICP Cell
Zarlink Semiconductor Inc.
MT90222/3/4
123
Description
Description
Description
Description
Data Sheet