MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 85

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:12
15:12
Bit #
Bit #
Bit #
15:8
11:8
11:8
7:4
3:0
7:4
3:0
...
7
6
1
0
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
...
R
R
Unused. Read 0’s.
TX FIFO Length IMA Group N+4.
Reserved. Write 0’s for normal operation.
TX FIFO Length IMA Group N
Unused. Read all 0’s.
Write a 1 will enable the generation of an interrupt from the frame indication for IMA
Group 7. A 0 will inhibit the generation of an interrupt.
Write a 1 will enable the generation of an interrupt from the frame indication for IMA
Group 6. A 0 will inhibit the generation of an interrupt.
....
Write a 1 will enable the generation of an interrupt from the frame indication for IMA
Group 1. A 0 will inhibit the generation of an interrupt.
Write a 1 will enable the generation of an interrupt from the frame indication for IMA
Group 0. A 0 will inhibit the generation of an interrupt.
Unused. Read 0’s.
TX FIFO Length Link N+8.
Reserved. Write 0’s for normal operation.
TX FIFO Length Link N.
0101
Table 24 - TX IMA Group FIFO Length Definition Register
groups 0,1,2 and 3 are used.
0x008B-0x0092 (8 reg)
1 register per 2 links. Link 0 is paired with link 8, link 1 is
0101
0x0093-0x0096 (4 reg)
1 register per 2 IMA groups. Group 0 is paired with Group 4, Group 1 is
0x0089 (1 reg)
Interrupt Enable register for the TX ICP Handler register.For MT90222 only
0000
paired with Group 5 and so on. For MT90222 only groups 0,1,2 and 3 are used.
paired with link 9 and so on.
Table 23 - TX Link FIFO Length Definition Register
Table 22 - TX IMA Frame Interrupt Enable Register
Zarlink Semiconductor Inc.
MT90222/3/4
85
Description
Description
Description
Data Sheet