MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 142
MT90222AG
Manufacturer Part Number
MT90222AG
Description
Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
Manufacturer
Zarlink Semiconductor
Datasheet
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Note 1 - For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access.
AC Electrical Characteristics - CPU Interface Intel Timing - Write Cycle
1
2
3
4
5
UP_D[15:0]
UP_A[11:0]
UP_R/W
(WRITE)
(READ)
UP_OE
UP_CS
UP_CS set-up time to UP_R/W
falling edge
Address and Data set up before
rising edge of UP_R/W
UP_AD, UP_CS and Data hold time
after UP_R/W rising edge
UP_R/W low after rising edge or
UP_CS
UP_CS high before next UP_CS low
Characteristics
t
ws
Figure 34 - CPU Interface Intel Timing - Write Access
Zarlink Semiconductor Inc.
Sym
t
t
t
t
t
ADH
CSH
MT90222/3/4
WH
WS
SU
ADDRESS VALID
DATA VALID
(see Note 1)
142
t
Min
su
10
1
4
1
2
Typ
t
adh
Max
t
csh
t
wh
system
Units
cycle
clock
ns
ns
ns
ns
Test Conditions
Data Sheet
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