PIC16C63A Microchip Technology, PIC16C63A Datasheet - Page 39

• Manufacturer Part Number: PIC16C63A
• Description: 28/40-Pin 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

5.0
The Timer1 module timer/counter has the following fea-
tures:
• 16-bit timer/counter
• Readable and writable (Both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• Reset from CCP module trigger
Timer1 has a control register, shown in Figure 5-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Figure 5-2 is a simplified block diagram of the Timer1
module.
Additional information on timer modules is available in
the
(DS33023).
FIGURE 5-1:
1998 Microchip Technology Inc.
(Two 8-bit registers; TMR1H and TMR1L)
bit7
bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
bit 3:
bit 2:
bit 1:
bit 0:
U-0
PICmicro
—
TIMER1 MODULE
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (F
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
U-0
—
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
Mid-Range
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
R/W-0
OSC
Reference
R/W-0
/4)
R/W-0
Manual,
PIC16C63A/65B/73B/74B
R/W-0
5.1
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 also has an internal “reset input”. This reset can
be generated by the CCP module (Section 7.0).
TMR1CS TMR1ON
R/W-0
Timer1 Operation
R/W-0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
read as ‘0’
DS30605A-page 39