PIC16C63A Microchip Technology, PIC16C63A Datasheet - Page 94

• Manufacturer Part Number: PIC16C63A
• Description: 28/40-Pin 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

PIC16C63A/65B/73B/74B
FIGURE 11-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT
11.14
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
11.15
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
For ROM devices, these values are submitted along
with the ROM code.
11.16
PIC16CXXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming volt-
age. This allows customers to manufacture boards with
unprogrammed devices, and then program the micro-
controller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS30277B).
DS30605A-page 94
Note 1:
Note:
INSTRUCTION FLOW
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction
fetched
Instruction
executed
CLKOUT(4)
2:
3:
4:
INT pin
OSC1
Program Verification/Code Protection
ID Locations
PC
In-Circuit Serial Programming
XT, HS or LP oscillator mode assumed.
T
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
Microchip Technology does not recom-
mend code protecting windowed devices.
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4
= 1024T
Inst(PC - 1)
PC
OSC
(drawing not to scale) This delay will not be there for RC osc mode.
Q1 Q2 Q3 Q4
Inst(PC + 1)
SLEEP
PC+1
Q1
Processor in
SLEEP
PC+2
T
OST
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
PC+2
Interrupt Latency
Dummy cycle
(Note 2)
PC + 2
Q1 Q2 Q3 Q4
1998 Microchip Technology Inc.
Inst(0004h)
Dummy cycle
0004h
Q1 Q2 Q3 Q4
Inst(0005h)
Inst(0004h)
0005h