PIC16C63A Microchip Technology, PIC16C63A Datasheet - Page 45

• Manufacturer Part Number: PIC16C63A
• Description: 28/40-Pin 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

7.0
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave Duty Cycle register. Table 7-1 shows the
timer resources of the CCP module modes.
The operation of CCP1 is identical to that of CCP2, with
the exception of the special trigger. Therefore, opera-
tion of a CCP module in the following sections is
described with respect to CCP1.
Table 7-2 shows the interaction of the CCP modules.
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 7-2:
FIGURE 7-1:
CCPx Mode CCPy Mode
Capture
Capture
Compare
PWM
PWM
PWM
1998 Microchip Technology Inc.
bit7
bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
U-0
—
CAPTURE/COMPARE/PWM
(CCP) MODULE(S)
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
0000 = Capture/Compare/PWM off (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1
11xx = PWM mode
U-0
—
Capture
Compare
Compare
PWM
Capture
Compare
INTERACTION OF TWO CCP MODULES
CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh)
CCPxX
R/W-0
and starts an A/D conversion (if A/D module is enabled))
CCPxY CCPxM3
Same TMR1 time-base.
The compare should be configured for the special event trigger, which clears TMR1.
The compare(s) should be configured for the special event trigger, which clears TMR1.
The PWMs will have the same frequency, and update rate (TMR2 interrupt).
None
None
R/W-0
R/W-0
CCPxM2
R/W-0
PIC16C63A/65B/73B/74B
CCPxM1 CCPxM0
R/W-0
CCP2 Module
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
Additional information on the CCP module is available
in the PICmicro
(DS33023).
TABLE 7-1:
Interaction
CCP Mode
Compare
Capture
PWM
R/W-0
bit0
CCP MODE - TIMER
RESOURCE
Mid-Range Reference Manual,
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n =Value at POR reset
read as ‘0’
Timer Resource
DS30605A-page 45
Timer1
Timer1
Timer2