PIC16C63A Microchip Technology, PIC16C63A Datasheet - Page 43

• Manufacturer Part Number: PIC16C63A
• Description: 28/40-Pin 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

6.0
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (Both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
• SSP module optional use of TMR2 output to gen-
Timer2 has a control register, shown in Figure 6-1.
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Figure 6-2 is a simplified block diagram of the Timer2
module.
Additional information on timer modules is available in
the
(DS33023).
FIGURE 6-1:
1998 Microchip Technology Inc.
erate clock shift
bit7
bit 7:
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
bit 2:
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
U-0
PICmicro
—
TIMER2 MODULE
Unimplemented: Read as '0'
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
R/W-0
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
Mid-Range
R/W-0
Reference
R/W-0
R/W-0
Manual,
PIC16C63A/65B/73B/74B
R/W-0
6.1
Timer2 can be used as the PWM time-base for PWM
mode of the CCP module.
The TMR2 register is readable and writable, and is
cleared on any device reset.
The input clock (F
1:4
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR reset,
TMR2 is not cleared when T2CON is written.
R/W-0
Watchdog Timer reset, or Brown-out Reset)
or
Timer2 Operation
R/W-0
1:16,
bit0
OSC
selected
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
/4) has a prescale option of 1:1,
read as ‘0’
by
DS30605A-page 43
control
bits