PIC16C63A Microchip Technology, PIC16C63A Datasheet - Page 41

• Manufacturer Part Number: PIC16C63A
• Description: 28/40-Pin 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

5.2
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 5-1 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 5-1:
TABLE 5-2:
Crystals Tested:
32.768 kHz
100 kHz
200 kHz
Note 1: Higher capacitance increases the stability
Address Name
0Bh,8Bh
0Ch
8Ch
0Eh
0Fh
10h
Legend:
Note 1: These bits are reserved, maintain as '0'.
Osc Type
1998 Microchip Technology Inc.
LP
These values are for design guidance only.
2: Since each resonator/crystal has its own
Timer1 Oscillator
of the oscillator but also increases the start-
up time.
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
INTCON
PIR1
PIE1
TMR1L
TMR1H
T1CON
Epson C-001R32.768K-A
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
100 kHz
200 kHz
32 kHz
Freq
CAPACITOR SELECTION
FOR THE TIMER1
OSCILLATOR
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
Bit 7
GIE
(1)
(1)
—
PEIE
ADIF
ADIE
Bit 6
—
33 pF
15 pF
15 pF
C1
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Bit 5
T0IE
(1)
(1)
33 pF
15 pF
15 pF
20 PPM
20 PPM
20 PPM
C2
INTE
Bit 4
(1)
(1)
PIC16C63A/65B/73B/74B
SSPIF
SSPIE
RBIE
Bit 3
5.3
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.4
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.
Note:
CCP1IE
CCP1IF
Bit 2
T0IF
Timer1 Interrupt
Resetting Timer1 using a CCP Trigger
Output
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TMR2IE
TMR2IF
Bit 1
INTF
TMR1IE
TMR1IF
Bit 0
RBIF
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on
POR,
BOR
DS30605A-page 41
Value on
all other
resets