MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 29

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

Advance Information
Multiple IDX systems are supported by allowing the IDX to either drive or receive an 8.192 MHz clock. The
master IDX in the system may supply C8 while the slave IDX derive their timing from the master. In a multi-
chassis application a slave IDX may be required to generate its own C10. C8 is distributed between master and
slave IDX devices and the PLL is then used to phase lock C10, C4 and C2 to the C8 input.
The MT90812 Expansion Bus can be supported with either an 8.192 MHz or 16.384 MHz clock when operating
at 8.192 Mb/s. When the input clock source is selected as 16.384 MHz either HMVIP and non-HMVIP mode
may be used.
In a multiple IDX system the slave IDX devices are supplied C8 from a master IDX. A watchdog timer on the
IDX allows the slave IDX to monitor the C8 input. In the event of the loss of the C8 clock the slave IDX can be
switched to be master IDX and supply C8 to the system. This provides redundancy for the clock source
allowing IDX operation to remain independent of the other IDX devices if necessary.
*Non-mux mode addresses for TCR, OCCR, INTE and INTS are 382
**C8 and F8 are bi-directional pads. They are used as inputs in C8 timing mode, otherwise as output pads.
9.1
The Input Timing Reference is selected setting CR1-0 and HMVIP bits in the Timing Control Register (TC)
described on page 55. One of five possible clock and frame pulse references, C4/F4, C8/F8, C8P, or C16/F8,
C16/HMVIP, can be selected, as listed in Table 9.
The MT90812 requires at least an 8.192 MHz clock internally. When the C4 input clock is selected the 8.192
MHz clock is derived from the PLL. C4 is not a valid clock reference when the PLL is disabled.
*02
*03
CR1,0
H
H
External
8.192 MHz
Crystal
00
01
10
11
11
PCOS,-,C10E,C8E,F8E,C4E,F4E,C2E
WDE,FPO,CR1-0,HMVIP,PE,PMS,PCS
Output Clock Control Register
Input Timing Reference
Timing Control Register
OSCo
HMVIP
C8**
C4i
F8**
FPi
0
1
x
x
x
C8P_C16
Figure 16 - Clock Control Functional Diagram
Clock Reference
C16 Non-HMVIP
C8
Table 9 - Clock Modes
C8P (default)
C16 HMVIP
C4
C8
PLL
WD
H
, 383
H
C8F
, 384
*04
*05
H
Interrupt Status Register
and 385
H
H
Interrupt Enable Register
C8F
Timing
Interface
C8FE
H
, respectively.
Frame Pulse Reference
No Frame Pulse
C8 Internal CLK
ST_CLK
EST_CLK_IN
EST_CLK_OUT
FPi (F8)
FPi(F4)
FPi(F4)
F8i
C10o
C8**
F8**
C4o
F4o
C2o
MT90812
25