MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 70

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

MT90812
The IT bit will be set for the duration of the tone added to the conference. Reading any of the CPC registers in
a particular conference, will show the IT bit set for that time.
Channel Attenuation is provided on incoming and outgoing channels in a conference. The incoming channel
attenuation is set in CMH for the specific conference party. The outgoing gain is applied to the output of the
conference block before it is written to the Data Memory output conference location.
Refer to “Conferencing” on page 18.
22.21 D-Channel Receive Interrupt Threshold (DRXIT)
The register is configured as follows:
The D-Channel Receiver Interrupt Threshold is specified in two ways depending on whether Message Length
Interrupt Mode or FIFO Level Interrupt Mode is used.
22.21.1 Message Length Interrupt Mode
An interrupt is generated when a message of N bits is received, where N is the message Length in bits
specified by D7-D0. D7 is the MSB. For example, 00
a bit length of 256.
The message length count is the number of bits between the start bit and the parity bit or stop bit.
22.21.2 FIFO Level Interrupt Mode
An interrupt is generated when there are N bytes in the FIFO, where N is specified by D5-D0. D5 is the MSB.
For example, 01
level of 32 bytes in the FIFO.
66
Read/Write Address is: 40
Reset Value is: 00
7-0
Bit
D7-D0
Name
H
corresponds to an interrupt level of 1 byte in the FIFO and 20
H
Message Length Interrupt Mode. D-Channel Receive Message Length 1-256 bits.
FIFO Level Interrupt Mode: D5-D0 used to specify FIFO Level of 1-32.
H
D7
7
D6
6
D5
5
D4
4
H
D3
3
corresponds to a bit length of 1 and FF
D2
2
Description
D1
1
D0
0
H
Advance Information
corresponds to an interrupt
H
corresponds to