MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 36

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

MT90812
will specify whether the received data will have a parity bit and consequently the receiver will perform a parity
check on the received data.
In FLI Mode, the start and stop bits and the parity bit can be enabled or disabled with the SE and PE bits in the
DRXC Control register, respectively. With the start and stop bits enabled, the start of the message is identified
by the first ‘0’ received after the DBR is enabled. When the start and stop bits are disabled, no parity check will
be performed (regardless of the status of PE bit) and the data will be transferred from the incoming TDM
stream to the RX FIFO following the RX being enabled.
11.1.1
There are four interrupts associated with the D-channel Receiver. They are listed in Table 11.
The DREE and DRXE bits in the “Interrupt Enable Register (INTE)” on page 57 enable/disable the above
interrupts.
The main difference in MLI and FLI modes is in determining when the interrupt occurs. In MLI mode the
interrupt occurs when the full message has been received. In FLI mode the interrupt occurs when the number
of bytes in the FIFO equals the trigger level. The “D-Channel Receive Interrupt Threshold (DRXIT)” register is
used to program when an interrupt occurs for either MLI or FLI Mode. In the latter mode, the interrupt is to
indicate that the FIFO level is attained and not necessarily the end of the message. In the former mode, the
interrupt solely indicates the end of the message.
As listed in Table 11 an interrupt is also triggered when one of the following error conditions occurs:
•
32
Interrupts
The RX FIFO is full and the next byte of data has been received and is to be transferred to the FIFO
then the overrun status bit is set and an interrupt occurs (RX overrun error).
DRX
DRE
OE
PE
SE
Receiver Interrupt Handling
DSTI
Register
DRXS
DRXS
DRXS
INTS
INTS
Serial to Parallel
Uport Read
Reference Page
Figure 22 - Data Flow for D-channel Receiver
Table 11 - D-Channel Receive Interrupts
page 56
page 56
page 68
page 68
page 68
DRXOUT = 43
Control Registers
Data Memory
Channel m
D-Channel Receive Message Length or FIFO Level
interrupt
D-Channel Receive FIFO Error. Status of error in DCHS
register.
Receive Overrun Error
Receive Parity Error
Receive Stop Bit Error
HEX
RX FIFO
RX
Description
DCHin CM 70H
Channel m
Advance Information
DBRX