MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 37

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

Advance Information
•
•
12.0 Transmitter Operation
Fig. 23 illustrates the data flow for the D-channel data in the transmit direction. A system write to the TX FIFO
buffer is performed by addressing the “D-Channel TX FIFO Input (DTXIN)” register at location 44
Control Register page. Up to 32 bytes can be written to the FIFO. The output of the DBTX is memory mapped
to Data Memory location 70
channel by programming Connect Memory Low as 70
As with the Receiver, the Transmitter also operates in two modes: MLIM and FLIM. The TX control register “D-
Channel TX Control (DTXC)” at location 45
for interrupt select, transmission rate at 1, 2, or 8 bits per frame, MLI or FLI mode, start and stop bit enable
(SE), parity enable (PE), and start transmission (ST). The transmission sequence starts when bit ST is set
followed by writing the first byte to the FIFO. The transmission bit order is determined from TXB0 bit in the “D-
Channel Receive Interrupt Threshold (DRXIT)” register. Refer to page 66 for a description on the transmission
bit order.
In MLI Mode, the Transmitter automatically appends the start and stop bits to an N byte message with an
optional parity bit. The status of SE bit has no effect on this mode but the PE bit specifies whether the message
to be transmitted requires a parity bit.
In FLI Mode, the status of SE and PE bits can provide three transmission methods. If the SE bit is disabled, the
Transmitter does not include start, parity and stop bits to the message regardless of the status of PE bit. If SE
is enabled, the user has the option of enabling or disabling the PE bit. The start, parity, and stop bits are
applied on a per byte basis.
The transmitted messages are always padded with stop bits for any remaining bits. For example in the case
where a byte long message is to be sent with start and stop bits and a data rate at 8 bits per frame, the
transmission of the message will take two frames and the stop bit will be in the second bit of the second frame
and the 3rd to 8th bits will be padded with stop bits.
The Transmitter operation also provides a message to be broadcast to several channels simultaneously. This is
accomplished by programming the Connect Memory of the intended outgoing channels all to 70
application for broadcasting messages might be to update displays on all phone sets.
The stop bit was not detected (RX stop bit error).
The status of the received parity bit did not equate to the calculated parity (RX parity bit error).
Uport Write
44
HEX
70
HEX
Control Registers
Data Memory
HEX
DTXIN
Figure 23 - Data Flow for D-channel Transmitter
. The output of the Transmitter can then be directed to the specified output
HEX
of the Control Register page is used to program the Transmitter
TX FIFO
DBTX
HEX
TX
for the intended output channel.
Parallel to Serial
Connect Memory
70
HEX
Output Stream
Channel m
MT90812
HEX
HEX
of the
. One
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