MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 31

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

Advance Information
The MT90812 generates C4o, F4o, C8, and F8 signals in either ST-Bus or GCI formats as selected by the FPO
bit in the Timing Control Register (TC). This selection is independent of the incoming frame synchronization
used.
9.2.5
As mention above, the clocks used for the local and expansion bus streams can be derived directly from the
input clock reference or from the PLL. Two bits are used to control this, the PLL Clock Select (PCS) bit in the
TC register and the PLL Clock Output Select (PCOS) bit in the Output Clocking Control Register (OCC).
Referring to Figure 16, “Clock Control Functional Diagram,” on page 25, the clock used for the STi/o0 and STi/
o1 serial streams, is STCLK. The clocks used for clocking in data and clocking out data on the Expansion Bus
are EST_CLK_IN and EST_CLK_OUT, respectively.
With PCS set high, EST_CLK_IN, STCLK and C4o are generated from the PLL. Otherwise they are derived
from the input clock. With the PCS set high, C4o and C10 are both supplied from the PLL for clock supply to the
MT9171/72/73 DNIC devices. The other advantage with PCS high allows for clocking in data at three quarters
into the bit cell on the 8Mb/s Expansion Bus.
With PCOS set high, EST_CLK_OUT and C8 (output) are generated from the PLL. Otherwise, they are derived
from the input clock. For example, with PCOS=0 in C8P timing mode, C8P is used to generate C8 (output) and
in C16 timing modes, C8 (output) is C16 divided by 2. When C4F4 is used as the timing reference, EST0/1, 4
and 8 Mb/s timing, as well as F8o and C8o, are generated from the PLL independent of the PCS and PCOS
settings.
9.3
As shown in Fig. 17, the PLL of the MT90812 consists of a Phase and Frequency Detector, Loop Filter, Voltage
Controlled Oscillator and Divider Circuit.
The Phase and Frequency Detector compares the reference signal selected by CR0-1 bits in the TC register,
with the feedback signal from the Divider circuit, and provides an error signal corresponding to the phase
difference between the two. This error signal is passed to the Loop Filter.
The Loop Filter is a second order low pass filter which operates in two modes, Master and Slave. These
modes are described in Section 9.3.1. The Voltage Controlled Oscillator receives the filtered signal from the
Loop Filter and based on its value, generates a corresponding digital output signal.
The Divider circuit uses the VCO output to generate five clock outputs, C10, C8, C8_75, C4 and C4_75. C10,
C8 and C4 are 10.29 MHz, 8.192 MHz and 4.096 MHz signals respectively. C8_75 and C4_75 are 8.192 MHZ
and 4.096 MHz signals with a 75/25% duty cycle. These two clock signals are used in the Serial Interface
Circuit for the Expansion Bus. Refer to Section 9.2.
The PLL is enabled with PE bit set in the Timing Control Register (TC). With the PLL off, C10 is disabled and
C4 as an input clock reference is not valid.
*02
H
Clock
Reference
WDE
Phase Lock Loop (PLL)
Selecting Timing from the Input Clock Reference or from the PLL
,
FPO
Timing Control Register
, CR1-0,
HMVIP
Frequency
Detector
Phase &
, PE, PMS,
PCS
Charge
Pump
Figure 17 - PLL Block Diagram
Loop
Filter
V to I
Controlled
Oscillator
Current
Divider
MT90812
C10
C8
C8_75
C4
C4_75
27