MT8VDDT6464HD Micron Semiconductor Products, MT8VDDT6464HD Datasheet - Page 11

• Manufacturer Part Number: MT8VDDT6464HD
• Description: (MT8VDDTxx64HD) 200-Pin DDR Sdram Sodimms
• Manufacturer: Micron Semiconductor Products

w w w . D a t a S h e e t 4 U . c o m
Commands
of available commands. For a more detailed descrip-
Table 8:
CKE is HIGH for all commands shown except SELF REFRESH
NOTE:
Table 9:
Used to mask write data; provided coincident with the corresponding data
09005aef806e1d28
DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
NAME (FUNCTION)
WRITE Enable
WRITE Inhibit
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A11 (128MB) or A0–A12 (256MB, 512MB ) provide row address.
3. BA0–BA1 provide device bank address; A0–A8 (128MB, 256MB) or A0–A9 (512MB), provide column address; A10 HIGH
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register;
The Truth Tables below provides a general reference
enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
bursts with auto precharge enabled and for WRITE bursts.
BA1 are “Don’t Care.”
BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (128MB) or A0–
A12 (256MB, 512MB) provide the op-code to be written to the selected mode register.
Commands Truth Table
DM Operation Truth Table
11
CS#
tion of commands and operations, refer to the 128Mb,
256Mb, or 512Mb DDR SDRAM component data sheet.
H
L
L
L
L
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MB, 256MB, 512MB (x64)
RAS#
X
H
H
H
H
L
L
L
L
CAS#
X
H
H
H
H
L
L
L
L
200-PIN DDR SODIMM
WE#
X
H
H
H
H
L
L
L
L
©2003 Micron Technology, Inc. All rights reserved.
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
DM
H
L
NOTES
6, 7
Valid
DQS
1
1
2
3
3
4
5
8
X