MT8VDDT6464HD Micron Semiconductor Products, MT8VDDT6464HD Datasheet - Page 9

• Manufacturer Part Number: MT8VDDT6464HD
• Description: (MT8VDDTxx64HD) 200-Pin DDR Sdram Sodimms
• Manufacturer: Micron Semiconductor Products

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Table 6:
NOTE:
Table 7:
09005aef806e1d28
DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN
LENGTH
1. For a burst length of two, A1
2. For a burst length of four, A2
3. For a burst length of eight, A3
4. Whenever a boundary of the block is reached within a
5. i = 8 for 128MB and 256MB;
BURST
element block; A0 selects the first access within the
block.
element block; A0
block.
element block; A0
block.
given sequence above, the following access wraps
within the block.
i = 9 for 512MB.
2
4
8
SPEED
-26A
-335
-262
-265
-202
A2 A1 A0
0
0
0
0
1
1
1
1
STARTING
ADDRESS
COLUMN
Burst Definition Table
CAS Latency (CL) Table
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
75 £ f £ 133
75 £ f £ 133
75 £ f £ 133
75 £ f £ 100
75 £ f £ 100
A0
–
–
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A1 select the first access within the
A2 select the first access within the
CLOCK FREQUENCY (MHZ)
CL = 2
ALLOWABLE OPERATING
ORDER OF ACCESSES WITHIN
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
SEQUENTIAL
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
–
–
–
Ai select the two-data-
Ai select the four-data-
Ai select the eight-data-
A BURST
75 £ f £ 166
75 £ f £ 133
75 £ f £ 125
75 £ f £133
75 £ f £133
CL = 2.5
INTERLEAVED
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
9
Operating Mode
MODE REGISTER SET command with bits A7–A11 (for
128MB), or A7–A12 (256MB, 512MB) each set to zero,
and bits A0–A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command
with bits A7 and A9–A11 (128MB), or A7 and A9–A12
(256MB, 512MB) each set to zero, bit A8 set to one, and
bits A0–A6 set to the desired values. Although not
required by the Micron device, JEDEC specifications
recommend when a LOAD MODE REGISTER com-
mand is issued to reset the DLL, it should always be
followed by a LOAD MODE REGISTER command to
select normal operating mode.
A12 are reserved for future use and/or test modes. Test
modes and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
Extended Mode Register
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 6, Extended Mode Register
Definition Diagram, on page 10. The extended mode
register is programmed via the LOAD MODE REGIS-
TER command to the mode register (with BA0 = 1 and
COMMAND
COMMAND
The normal operating mode is selected by issuing a
All other combinations of values for A7–A11, or A7–
The extended mode register controls functions
DQS
DQS
CK#
CK#
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
CK
CK
128MB, 256MB, 512MB (x64)
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
200-PIN DDR SODIMM
TRANSITIONING DATA
CL = 2
CL = 2.5
NOP
NOP
T1
T1
©2003 Micron Technology, Inc. All rights reserved.
T2
NOP
NOP
T2
T2n
T2n
DON’T CARE
T3
NOP
NOP
T3
T3n
T3n