MT8VDDT6464HD Micron Semiconductor Products, MT8VDDT6464HD Datasheet - Page 21

• Manufacturer Part Number: MT8VDDT6464HD
• Description: (MT8VDDTxx64HD) 200-Pin DDR Sdram Sodimms
• Manufacturer: Micron Semiconductor Products

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DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55. Functionality is uncertain when
operating beyond a 45/55 ratio. Figure 7, Derating
Data Valid Window (
ating curves for duty cycles ranging between 50/
50 and 45/55.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
the input must:
a. Sustain a constant slew rate from the current
t
QH =
AC level through to the target AC level, V
or V
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
IH
t
HP -
(AC).
50/50
3.750
2.500
3.400
t
QHS). The data valid window derates
NA
49.5/50.5
3.700
-335 @
-262/-26A/-265 @
-202 @
-262/-26A/-265 @
-202 @
t
3.350
2.463
t
QH -
HP (
t
t
t
CK = 6ns
CK = 10ns
CK = 8ns
t
Figure 7: Derating Data Valid Window
CK/2),
t
DQSQ), shows the der-
3.650
49/51
2.425
3.300
t
t
t
RFC [MIN]) else
CK = 10ns
CK = 7.5ns
t
DQSQ, and
48.5/52.5
3.600
2.388
3.250
IL
(
t
QH -
(AC)
t
48/52
3.550
QH
2.350
3.200
Clock Duty Cycle
21
t
DQSQ)
47.5/53.5
3.500
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
30.
2.313
3.150
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
be ³ 1V/ns (2V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4V/ns, functionality is uncertain.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
t
minimum actually applied to the device CK and
CK/ inputs, collectively during bank active.
DH for each 100mv/ns reduction in slew rate. If
HP min is the lesser of
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
128MB, 256MB, 512MB (x64)
maintain at least the target DC level, V
or V
47/53
3.450
must not vary more than 4 percent if CKE is
2.275
3.100
IH
(DC).
46.5/54.5
200-PIN DDR SODIMM
3.400
2.238
3.050
3.350
46/54
©2003 Micron Technology, Inc. All rights reserved.
2.200
3.000
t
CL minimum and
45.5/55.5
3.300
2.163
2.950
3.250
45/55
t
DS and
IL
2.125
2.900
(DC)
t
CH