MT8VDDT6464HD Micron Semiconductor Products, MT8VDDT6464HD Datasheet - Page 23

• Manufacturer Part Number: MT8VDDT6464HD
• Description: (MT8VDDTxx64HD) 200-Pin DDR Sdram Sodimms
• Manufacturer: Micron Semiconductor Products

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DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN
35. The voltage levels used are derived from a mini-
36. V
37. V
38. This maximum value is derived from the refer-
39. For slew rates greater than 1V/ns the (LZ) transi-
40. During initialization, V
41. The current Micron part operates below the slow-
Figure 10: Reduced-Drive Pull-Down
80
70
60
50
40
30
20
10
0
0.0
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
pulse width £ 3ns and the pulse width can not be
greater than 1/3 of the cycle rate. V
V
pulse width can not be greater than 1/3 of the
cycle rate.
enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
310ps less for
(MAX) will prevail over
(MAX) condition.
t
tion will start about 310ps earlier.
be equal to or less than V
V
even if V
42 W of series resistance is used between the V
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
DQSCK (MIN) +
IH
IL
DD
TT
(MIN) = -1.5V for a pulse width £ 3ns and the
overshoot: V
and V
may be 1.35V maximum during power up,
DD
DD
0.5
DD
level and the referenced test load. In
/V
Characteristics
Q must track each other.
DD
t
HZ(MAX) and the last DVW.
Q are 0V, provided a minimum of
t
IH
RPRE (MAX) condition.
1.0
t
LZ (MIN) will prevail over
(MAX) = V
V
DD
OUT
t
DD
DQSCK (MAX) +
(V)
Q, V
+ 0.3V. Alternatively,
1.5
TT
DD
, and V
Q + 1.5V for a
IL
undershoot:
2.0
Minimum
REF
t
RPST
must
t
HZ
TT
2.5
23
42.
43. For the -335, -262, -26A, and -265, I
44. Random addressing changing and 50 percent of
45. Random addressing changing and 100 percent of
46. CKE must be active (high) during the entire time a
47. I
48. Whenever the operating frequency is altered, not
49. Leakage number reflects the worst case leakage
50. The -335 module speed grade, using the -6R speed
-10
-15
-20
-25
-30
-35
-40
-45
-50
-5
0
0.0
Figure 11: Reduced-Drive Pull-Up
t
fied to be 35mA at 100 MHz.
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
driven to a valid high or low logic level. I
similar to I
address and control inputs to remain stable.
Although I
I
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).
possible through the module pin, not what each
memory device contributes.
device, has V
RAP
REF later.
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MB, 256MB, 512MB (x64)
2N specifies the DQ, DQS, and DM to be
2
0.1
F
³
is “worst case.”
t
RCD. Does not apply to -335 speed grade.
0.2
DD
200-PIN DDR SODIMM
Characteristics
DD
DD
0.3
2
F
2
, I
(MIN) = 2.4V.
F
DD
0.4
except I
V
2
DD
N
Q - V
0.5
, and I
©2003 Micron Technology, Inc. All rights reserved.
OUT
(V)
0.6
DD
DD
2
Q
0.7
2
DD
Q
specifies the
are similar,
0.8
3
N
Minimum
is speci-
DD
0.9
2
Q
1.0
is