MT8VDDT6464HD Micron Semiconductor Products, MT8VDDT6464HD Datasheet - Page 18

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MT8VDDT6464HD

Manufacturer Part Number
MT8VDDT6464HD
Description
(MT8VDDTxx64HD) 200-Pin DDR Sdram Sodimms
Manufacturer
Micron Semiconductor Products
Datasheet
www.DataSheet4U.com
Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC
Notes: 1–5, 12–15, 29, 50; notes appear on pages 20–23; 0°C £ T
09005aef806e1d28
DD8C16_32_64x64HDG_B.fm - Rev. B 7/03 EN
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per
access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge
command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command
delay
Operating Conditions (-26A, -265, and -202)
CL=2.5
CL=2
128MB
256MB/ 512MB
SYMBOL
t
t
t
t
t
DQSCK
WPRES
t
t
t
t
t
DQSQ
t
t
t
18
DQSH
t
WPRE
WPST
DIPW
DQSL
DQSS
t
t
t
t
t
t
t
RPRE
MRD
RPST
t
t
t
WTR
t
t
t
t
DSH
t
t
t
t
QHS
RCD
RRD
t
RAS
RAP
t
t
t
DSS
t
t
t
RFC
QH
WR
AC
CH
DH
CK
CK
DS
HP
HZ
IH
IH
RC
CL
LZ
IS
IS
RP
A
F
S
F
S
£ +70°C; V
7.5/10
-0.75
-0.75
-0.75
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN
0.45
0.45
1.75
0.35
0.35
0.75
0.90
0.90
0.25
t
128MB, 256MB, 512MB (x64)
7.5
0.5
0.5
0.2
0.2
0.9
0.4
0.4
15
40
20
65
75
20
20
15
15
RAS(MIN) - (burst length *
1
1
0
1
-26A/-265
t
HP -
t
CH,
DD
, V
t
120,000
t
QHS
CL
MAX
+0.75
+0.75
+0.75
DD
0.55
0.55
1.25
0.75
0.5
1.1
0.6
0.6
13
13
Q = +2.5V ±0.2V
200-PIN DDR SODIMM
MIN
0.45
0.45
0.35
0.35
0.75
0.25
-0.8
-0.8
-0.8
0.6
0.6
0.2
0.2
1.1
1.1
1.1
1.1
0.9
0.4
0.4
10
16
40
20
70
80
20
20
15
15
8
2
0
1
t
HP -
t
CH,
-202
©2003 Micron Technology, Inc. All rights reserved.
120,000
t
t
MAX
t
QHS
CK/2)
+0.8
0.55
0.55
+0.8
1.25
CL
+0.8
0.6
1.1
0.6
0.6
13
13
1
UNITS
t
t
t
t
t
t
t
t
t
t
t
t
ns
CK
CK
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
ns
CK
ns
CK
NOTES
41, 48
41, 48
23, 27
23, 27
22, 23
16, 38
16, 39
22, 23
18, 19
26
26
27
30
12
12
12
12
31
46
38
17

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