IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 11

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

TxREF clock signal.
This signal asserts high when a cell is transferred over the bus, and will
stay high for 2
seconds.
the MPHY Cell-Level Handshake with one TCLAV as described in the
UTOPIA Level 2 specification.
address is analyzed and extracted by the 77V011. The subport address
is then interleaved with the Null PHY subport address (0x1F) and output
on the TxADDR[4:0] bus to query the corresponding PHY port. Upon
detecting a high TCLAV the 77V011 will assert TENB low, TSOC and the
first valid byte/word of data. The current PHY subport address will be
Mode Select
IDT77V011
TxREF is a 8KHz reference clock output generated from REFCLK.
REFCLK is a 8KHz reference clock input used to generate the
TxLED indicates if there is activity on the transmit UTOPIA 2 bus.
TxPRTY is a parity bit for TxDATA[15:0] bus.
The TxADDR[4:0] bus is fully UTOPIA Level 2 compliant and follows
When a cell is transferred on the transmit DPI interface the subport
22
TCLK cycles. AT 40MHz this is approximately 0.1
8006
RxADDR[4:0]
RxADDR[4:0]
RxDATA[7:0]
RxDATA[7:0]
(output)
(output)
(output)
RCLAV
(output)
(output)
(output)
RCLAV
(input)
RSOC
(input)
RCLK
RENB
(input)
(input)
RSOC
(input)
RCLK
RENB
(input)
5
1
1F
1E
2
1F
6
1
1
47
1F
UTOPIA 2 Size 0 - 1
Figure 3 Polling Sequence with no Cell Transfer in Progress
4
Figure 4 Polling Sequence with Cell Transfer in Progress
48
1F
5
1
Table 2 UTOPIA 2 Receive Register Table
49
1F
2
5
11 of 43
50
1F
6
2
Defined by pin Selects the size of the UTOPIA 2 transmit and receive data bus.
output on the TxADDR[4:0] bus until another cell enters the 77V011 on
the transmit DPI interface. When a cell is detected on the transmit DPI
interface and a cell transfer is in progress on the transmit UTOPIA 2
interface, the subport is extracted and output on the TxADDR[4:0] bus,
interleaved with the Null PHY subport address, to query the new PHY
port. Once the current cell transfer on the transmit UTOPIA 2 interface is
complete and the new PHY port has responded, the new cell will be
transferred on the transmit UTOPIA 2 interface.
between back to back cells when switching is being done without a TAG,
and there is a maximum five clock cycle delay if a four byte TAG is being
used. There is a maximum three clock cycle delay between back to back
cells in 16-bit UTOPIA mode without a TAG, and a maximum five clock
cycle delay if a four byte TAG is being used.
Interface. In-Stream™ programming cells are used to program the regis-
ters, which are described in the UTOPIA 2 Transmit Register Table.
1F
51
3
6
With an 8-bit UTOPIA bus there is a maximum one clock cycle delay
There are several registers associated with the UTOPIA 2 Transmit
1F 1F
3
6
52
1A
"0" 8-bit UTOPIA 2 transmit and receive data bus, "1" 16-bit
UTOPIA 2 transmit and receive data bus.
1F
53
1B
6
1B
1F
7
1C
1F
1
1
7
8
1F
1C
5348drw0
5348drw0
2
2
.
March 15, 2001