IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 5

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

TxDATA [11]
TxDATA [12]
TxDATA [13]
TxDATA [14]
TxDATA [15]
TSOC
TCLAV
TENB
TxADDR[0]
TxADDR[1]
TxADDR[2]
TxADDR[3]
TxADDR[4]
TxLED
TCLK
TxPRTY
REFCLK
TxREF
EECLK
EECS
EEDIN
EEDOUT
BMODE
MBUS[0]
MBUS[1]
IDT77V011
2
143
142
141
140
134
126
138
129
130
131
132
133
137
128
139
125
16
50
49
47
48
70
67
66
O
O
O
O
O
O
I
O
O
I
O
I
O
I
O
I
O
O
O
O
I
O
O
O
I
O
I
O
I
O
I
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Reset
Normal
Reset
Normal
Reset
Normal
Reset
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
UTOPIA 2 Address Bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[1]).
Reset
UTOPIA 2 Address bus. Upper 64 bytes used for 32 address pointers describing PHY's.
Utility Bus Utility bus PHY chip select (CS[2]).
Reset
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
8-bit or 16-bit UTOPIA 2 output data bus used to transfer data to a PHY device. When in 8-bit mode use
TxDATA [7:0].
UTOPIA 2 Transmit Start of Cell marker.
UTOPIA 2 Transmit Cell Available.
UTOPIA 2 Transmit Enable.
UTOPIA 2 Transmit Address Bus [LSB].
Subport Byte Location. Indicates what byte the Tx and Rx Subport Address is located in [LSB].
UTOPIA 2 Transmit Address Bus [LSB+1].
Subport Byte Location. Indicates what byte the Tx and Rx Subport Address is located in [LSB+1].
UTOPIA 2 Transmit Address Bus [LSB+2].
Subport Byte Location. Indicates what byte the Tx and Rx Subport Address is located in [MSB].
UTOPIA 2 Transmit Address Bus [LSB+3].
Initialize from EEPROM. Selects whether five bytes of EEPROM are to be written to In-Stream™ Cell
Header and In-Stream™ Subport. "0" do not write five byte value, "1" write five byte value from EEPROM.
UTOPIA 2 Transmit Address Bus [MSB].
UTOPIA 2 Transmit LED.
UTOPIA 2 Transmit Clock.
Parity for DTxDATA [15:0].
8 KHz reference clock used to generate TxREF.
8KHz reference clock used by PHY.
EEPROM Clock.
EEPROM Chip Select.
Serial Input from the EEPROM.
Serial Output to the EEPROM.
Bus Mode. Selects Motorola or Intel bus mode. "0" selects Motorola, "1" selects Intel.
TxSIZE[0] - Number of bytes to remove from cell in transmit direction (LSB).
TxSIZE[1] - number of bytes to remove from cell in transmit direction (LSB + 1).
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March 15, 2001