IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 32

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

1 R W L I L F
1 R W L I L F D D D D W L R
1 R W L I L F
1 R W L I L F
be generated by the 77V011.
detected on the external PHYINT pin, or if an Address Range Error is
encountered. A second Event Notification cell will be generated if the
interrupt is not cleared within 25ms of when it occurred. Additional Event
Notification cells will be generated every 12ms thereafter until the inter-
rupt is cleared. A new event will not be reported until the related interrupt
has been cleared. It is up to the CPU to clear the interrupt, or to notify
higher layers that an interrupt has occurred. The interrupts are cleared
by writing a one to the PHY Interrupt or Address Range Error bits in the
Status register. Writing a one will clear the interrupt and reset the
register bit to zero.
Request bit is set to a one. Reply Notification cells enable the CPU to
keep status of its command cells.
, Q W H
, Q W H
, Q W H
, Q W H U U U U S S S S U U U U H W L
interrupt occurred.
Mask register determine if a Event Notification cell will be generated
when an interrupt is detected. The 77V011 will not generate a Event
Notification cell when an interrupt occurs if the register is set to the
default of zero, and will generate a Event Notification cell if set to a one.
to determine if it is set or not set. An Event Notification cell is not gener-
ated when this bit is set, and no action needs to be taken by the CPU.
However, the bit must be cleared, by writing a zero to it, in order to
detect additional cells that have been dropped.
Notification
Mask
Status
Timeout
Status
IDT77V011
There are two types of Notification cells, Event and Reply, that can
The 77V011 will generate an Event Notification Cell if an interrupt is
The 77V011 will generate a Reply Notification cell if the Acknowledge
When an interrupt occurs the Status register will indicate where the
The PHY Interrupt Mask and Rx Address Error bits of the Notification
The Tx Cell Drop bit of the Status register must be polled by the CPU
H W L
H W L Q Q Q Q J D Q G & O H D U L Q J ,
H W L
W L R Q Q Q Q & H O O
W L R
W L R
8008
8009
800A
J D Q G & O H D U L Q J ,
J D Q G & O H D U L Q J ,
J D Q G & O H D U L Q J , Q Q Q Q W H W H W H W H U U U U U U U U X S W V
& H O O
& H O O
& H O O
0
0
0
PHY
Interrupt
Mask
PHY
Interrupt
PHY
Interrupt
Status
0 - 1
0 - 1
0 - 1
Table 21 Interrupt Register Table
X S W V
X S W V
X S W V
0
0
0
32 of 43
Timeout Status register indicate that the interrupt occurred more than
25ms ago. This is a read only register used to verify that the interrupts
are being cleared by the CPU. Once an interrupt is detected the 77V011
will monitor the appropriate Status register bit to determine if the inter-
rupt is cleared. The 77V011 will generate a Event Notification cell, mask
bit must be set to a one, if the interrupt is not cleared within 25ms of
when the interrupt occurred and will set the Timeout Status bit. It will
generate additional Event Notification cells on 12ms intervals, thereafter,
until the interrupt is cleared. It is the CPU's responsibility to clear the
interrupt and/or notify higher layers that an interrupt has been encoun-
tered. The interrupt is cleared by the CPU writing a one to the appro-
priate Status register bit. Writing a one will clear the interrupt and reset
the register bit back to zero.
& H
& H
& H
& H O O O O O $ F F R X Q W L Q J
the counters are set to zero and will increment by one each time a cell is
received or transmitted over the UTOPIA interface. The counter values
are stored in the UTOPIA Tx and Rx Cell Counter registers and can be
read at any time. The counters will roll over once the maximum cell
count is reached.
0 L V
0 L V
0 L V
0 L V F F F F     ) ) ) ) H H H H D D D D W X W X W X W X U U U U H V H V H V H V
CNTRL_B, that can be connected to an external device for system
design engineer usage. Both of these signals are low after reset. There
is also a register associated with each control pin signal, which is
described in the Misc. Register Table.
The PHY Interrupt Status and Address Error Status bits of the
See Interrupt Register Table for description of interrupt registers.
The transmit and receive cell counters are always enabled. At reset
The 77V011 offers two external control pins, CNTRL_A and
Mask interrupt notification. "0" no Event Notification cell will be generated
when a PHY interrupt occurs, "1" generate Event Notification cell when a
PHY interrupt occurs.
When a interrupt occurs on the PHYINT pin this bit will be set to a one. "0"
no interrupt detected, "1" PHY interrupt detected.
Indicates that a PHY interrupt occurred more than 25ms ago, and the
PHY Interrupt bit of the Status register has not been cleared. This bit will
return to zero once the interrupt is cleared. "0" no PHY interrupt detected,
"1" interrupt occurred more than 25ms ago and has not been cleared.
O $ F F R X Q W L Q J
O $ F F R X Q W L Q J
O $ F F R X Q W L Q J
March 15, 2001