IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 12

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

Configuration 1
Configuration 2
Configuration 3
Status
IDT77V011
TxDATA[7:0]
TxDATA[7:0]
TxADDR[4:0]
TxADDR[4:0]
8001
8002
8003
8009
(output)
(output)
(output)
(output)
(output)
(output)
(output)
(output)
TCLAV
TCLAV
(output)
TSOC
(output)
TSOC
(input)
(input)
TCLK
TENB
TCLK
TENB
47
04
1B
0
[1:0]
[6:2]
[7:0]
2
48
1F
1F
Figure 6 Back-to-Back Cell Transfer on transmit UTOPIA 2 Bus
Figure 5 Single Cell Transfer with no Cell Transfer in Progress
Drop Tx Cell
Stall Tx
Max Subports
Stall Tx Cycles
Tx Cell Dropped
49
1B
1B
Table 3 UTOPIA 2 Receive Register Table
1F
1F
50
0
0 - 1
0x2
0x00 - 0x1E
0x00 - 0xFF
0 - 1
12 of 43
1B
1B
1
51
46
0
0x0
0x1E
0xFF
0
1F
1F
47
52
1B
1B
Drop a cell with an invalid subport address. "0" do not drop
the cell, "1" drop the cell.
Selects whether or not to stall the pipeline if the PHY trans-
mit FIFO is full. "0" drop cell, "1" stall pipeline indefinitely, "2"
stall pipeline for Stall Cycles.
Indicates the maximum subport address value for the
PHY(s) connected to the transmit UTOPIA 2 interface.
Number of TCLK cycles the interface has to stall the pipe-
line when the PHY transmit FIFO is full. This field is valid
only if the Stall Tx for Stall Cycles option is selected.
Indicates if any cells have been dropped at the transmit
UTOPIA 2 interface. This is a status indicator for the Stall Tx
bit of the Configuration 2 register. "0" no cells have been
dropped, "1" a cell was dropped because the PHY did not
respond.
53
48
1F
1F
49
1B
1B
50
1
1F
1F
5348drw07
5348drw08
1B
1B
51
2
.
.
March 15, 2001