IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 13

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

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designed to transfer ATM cells between two devices. The 77V011 DPI
interface will support either a 4-bit wide data bus (DPI-4) or an 8-bit wide
data bus (DPI-8). There are separate transmit and receive interfaces,
with all signals being sampled on the rising edge of their respective
clock.
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to the IDT SWITCHStAR or other DPI device. It supports either a 4-bit or
8-bit Output Data Bus (DRxDATA[7:0]) and follows the standard DPI
timing characteristics as described in the DPI specification. Other
signals associated with this interface are DPI Receive Start of Frame
(DRxFRM), and DPI Receive Clock (DRxCLK).
Depending on the DPI mode selected this clock will be either an input or
an output. In Normal Mode DRxCLK is an input to the 77V011, and its
frequency must be less than or equal to SYSCLK. In Switch Mode
DRxCLK is a continuous clock generated by the 77V011, with its
frequency being equal to SYSCLK. There is no flow control in Switch
mode, as it is assumed that the IDT SWITCHStAR will be able to accept
all incoming cells (non-blocking). Programming the clock direction is
done at reset.
condition of MGMT[3] being stored in the DPI Mode bit of the Mode
Select register. Setting MGMT[3] ="0" selects Switch Mode (output),
while setting MGMT[3] ="1" selects Normal Mode (input).
condition of MBUS[10] being stored in the DPI Size bit of the Mode
Mode Select
IDT77V011
The Data Path Interface (DPI) is a synchronous bus interface
The DPI Receive Interface is used to transfer cells from the 77V011
DRxCLK operates at a frequency less than or equal to SYSCLK.
The DPI mode is selected with the MGMT[3] signal at reset, with the
The DPI bus size is selected with the MBUS[10] pin at reset, with the
DRxCLK
DRxFRM
DRxDATA[3:0]
(output)
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output)
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(input/
(output)
8006
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0
1
Figure 7 Nibble Mode One Cell Transfer on Receive DPI Bus
DPI Size
DPI Mode
0
Table 4 UTOPIA 2 Receive Register Table
0 - 1
0 - 1
1
13 of 43
Defined by pin Selects the size of DPI data bus. "0" 4-bit DPI transmit and
Defined by pin Selects DRxCLK direction. "0" switch mode (output), "1" nor-
Select register. Setting MBUS[10] ="0" selects a 4-bit data bus, while
setting MBUS[10] ="1" selects an 8-bit data bus.
cycle long and is asserted high one DRxCLK cycle before the first
nibble/byte of valid data.
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SWITCHStAR or other DPI device to the 77V011. It supports either a 4-
bit or 8-bit Input Data Bus (DTxDATA[7:0]) and follows the standard DPI
timing characteristics as described in the DPI specification. Other
signals associated with this interface are DPI Transmit Start of Frame
(DTxFRM) and DPI Transmit Clock (DTxCLK).
stopped to control data flow to the PHY device.
cycle long and is asserted high one DTxCLK cycle before the first valid
nibble/byte of data.
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and receive of the UTOPIA interface to the 4 or 8-bit transmit and
receive of the DPI interface.
while in 8-bit DPI mode cell formatting is done little endian to match the
IDT 77V400 Switching Memory. The UTOPIA to DPI Conversion Table
illustrates how the 77V011 performs cell formatting in 4 and 8-bit DPI
mode.
2
DRxFRM is the start of frame marker. This signal is one DRxCLK
The DPI Transmit Interface is used to transfer cells from the IDT
DTxCLK operates at a frequency equal to SYSCLK. DTxCLK can be
DTxFRM is the start of frame marker. This signal is one DTxCLK
Byte swapping must be performed to convert the 8 or 16-bit transmit
In 4-bit DPI mode cell formatting is big endian, or upper nibble first,
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3
receive data bus, "1" 8-bit DPI transmit and receive data bus.
mal mode (input).
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103
104
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105
March 15, 2001
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