IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 41

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

Pin Controls
UTOPIA Rx Cell
Counter byte 3
UTOPIA Rx Cell
Counter byte 2
UTOPIA Rx Cell
Counter byte 1
UTOPIA Rx Cell
Counter byte 0
UTOPIA Tx Cell
Counter byte 3
UTOPIA Tx Cell
Counter byte 2
UTOPIA Tx Cell
Counter byte 1
UTOPIA Tx Cell
Counter byte 0
Subport
Configuration 2
Rx Subport Position
IDT77V011
801A
801B
801C
801D
801E
801F
8020
8021
8022
8023
8024
0
1
2
3
4
5
6
7
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[2:0]
[7:3]
[2:0]
[5:3]
[7:6]
Override Pin
Configuration
Control A
Control B
EEPROM Mux
Select
EEPROM Clock
Out
EEPROM Chip
Select
EEPROM Out
EEPROM In
Rx Cell Counter
[31:24]
Rx Cell Counter
[23:16]
Rx Cell Counter
[15:8]
Rx Cell Counter
[7:0]
Tx Cell Counter
[31:24]
Tx Cell Counter
[23:16]
Tx Cell Counter
[15:8]
Tx Cell Counter
[7:0]
Rx Subport
Width
Not Used
Rx Byte Location Defined by
Rx Bit Location
Not Used
Table 25 Internal Register Map (Part 4 of 4)
0
0
0x5
0
0
0
0
0
0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x5
pin
41 of 43
"Enables writing to pin configurable registers during normal operation. "0"
pin configurable registers are read only, "1" pin configurable registers are
read/write registers."
"Stores condition of Control A pin. "0" CNTRL_A = "0", "1" CNTRL_A = "1"."
"Stores condition of Control B pin. "0" CNTRL_B = "0", "1" CNTRL_B = "1"."
"Indicates if the EEPROM interface will be connected to the internal logic or
the EEPROM registers. "0" connected to internal logic, "1" connected to
EEPROM registers."
"EEPROM clock when EEPROM interface is connected to the EEPROM
registers. "0" clock low, "1" clock high."
"EEPROM chip select when EEPROM interface is connected to the
EEPROM registers. "0" EEPROM interface is selected, "1" EEPROM inter-
face is not selected."
EEPROM serial output when EEPROM interface is connected to the
EEPROM registers.
EEPROM serial input when EEPROM interface is connected to the
EEPROM registers.
Counter for cells transferred on the receive UTOPIA 2 bus. This counter will
wrap around once the maximum cell count is reached.
Counter for cells transferred on the receive UTOPIA 2 bus. This counter will
wrap around once the maximum cell count is reached.
Counter for cells transferred on the receive UTOPIA 2 bus. This counter will
wrap around once the maximum cell count is reached.
Counter for cells transferred on the receive UTOPIA 2 bus. This counter will
wrap around once the maximum cell count is reached.
Counter for cells transferred on the transmit UTOPIA 2 bus. This counter will
wrap around once the maximum cell count is reached.
Counter for cells transferred on the transmit UTOPIA 2 bus. This counter will
wrap around once the maximum cell count is reached.
Counter for cells transferred on the transmit UTOPIA 2 bus. This counter will
wrap around once the maximum cell count is reached.
Counter for cells transferred on the transmit UTOPIA 2 bus. This counter will
wrap around once the maximum cell count is reached.
Programs how many bits will be used for subport addressing in the receive
direction.
Indicates what byte of the receive cell header the subport starts in. The sub-
port address can cross the byte boundary.
Indicates what bit of the byte defined by the Rx Byte Location bits of the Rx
Subport Position register the MSB of the receive subport address starts.
The subport address can cross the byte boundary.
March 15, 2001