IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 7

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

MDATA[3]
MDATA[4]
MDATA[5]
MDATA[6]
MDATA[7]
MGMT[1]
MGMT[2]
MGMT[3]
MGMT[4]
MGMT[5]
PHYRST
PHYINT
SYSRST
SYSCLK
CTRL_A
CTRL_B
Vcc
GND
IDT77V011
84
85
86
87
88
77
76
75
69
78
74
71
46
45
53
52
1,10,18,30,
37,43,54,68,
73,80,90,100,
109,114,124,
136
9,17,28,36,
44,51,62,72,
79,89,99,108,
113,123,127,
135,144
I/O
I/O
I/O
I/O
I/O
O
O
I
O
I
I
O
O
I
I
I
O
O
Power
Ground
UTOPIA 2 Management interface data bus [LSB+3].
Utility Bus Utility Bus address and data bus [LSB+3].
UTOPIA 2 Management interface data bus [LSB+4].
Utility Bus Utility Bus address and data bus [LSB+4].
UTOPIA 2 Management interface data bus [LSB+5].
Utility Bus Utility Bus address and data bus [LSB+5].
UTOPIA 2 Management interface data bus [LSB+6].
Utility Bus Utility Bus address and data bus [LSB+6].
UTOPIA 2 Management interface data bus [MSB].
Utility Bus Utility Bus address and data bus [MSB].
UTOPIA 2 Validates Read or Write operation on Management interface (SEL).
Utility Bus Utility bus PHY Chip Select (CS[0]).
UTOPIA II Management interface Read or Data Strobe (RD/DS).
Utility Bus Utility bus read (RD).
Reset
UTOPIA 2 Management interface Write or Read/Write (WR/RW).
Utility Bus Utility bus Write (WR).
Reset
UTOPIA 2 Management interface Ready or Data Acknowledge (RDY/DTACK).
Utility Bus No functionality.
UTOPIA II No functionality.
Utility Bus Utility Bus Address Latch Enable (ALE).
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
MMODE - Selects what type of management mode interface to use. "0" selects Utility Bus style, "1" selects
UTOPIA 2 style.
MGMT[3] - Selects clock direction for DRxCLK. "0" DRxCLK is an output, "1" DRxCLK is an input.
PHY Reset. Resets the PHY device attached to the 77V011.
PHY Interrupt. Phy layer interrupt with open drain active low output.
System Reset. Resets the 77V011 and the PHY device(s) attached to it.
System Clock.
Control A for system engineering usage. This signal is Low after reset.
Control B for system engineering usage. This signal is Low after reset.
3.3V Power supply pins.
Ground pins.
7 of 43
March 15, 2001