IDT77V400 Integrated Device Technology, IDT77V400 Datasheet - Page 18

• Manufacturer Part Number: IDT77V400
• Description: 1.24 Gbps Switching Memory **not Recommended For New Designs**
• Manufacturer: Integrated Device Technology

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configure the PHY registers. Read and write commands are sent to the
PHY with In-Stream™ programming cells.
to be used as defined by the UTOPIA Level 2 specification. Setting
BMODE ="0" selects the Motorola style, while setting BMODE ="1"
selects the Intel mode.
internal registers of a particular PHY device. The addressing scheme of
what PHY and register address is user definable. An example would be
to use the upper five bits (MBUS[11:7]) for the subport number and the
lower seven bits (MBUS[6:0]) for the PHY register address.
from or write data to a PHY device.
the addressed location on the data bus when BMODE = "1", and when
BMODE = "0" it is an active low enable used to read data from the PHY
layer, or strobe write data to the PHY.
addressed location when BMODE = "1", and when BMODE = "0" it
defines the current transaction as a read, if equal to one, or a write, if
equal to zero.
MDATA[7:0] bus is complete.
asserted by writing to the PHY Reset bit in the PHY Reset register.
IDT77V011
The UTOPIA 2 Management interface is used to access and
BMODE selects the type of UTOPIA 2 Management Mode interface
MBUS[11:0] are address bits in this mode and are used to access the
MDATA[7:0] is a byte wide bi-directional data bus used to read data
MGMT[2] is an active low signal used as an enable to read data from
MGMT[3] is an active low write enable used to write data to an
MGMT[4] is an active low signal that indicates when a transfer on the
PHYRST is an active low PHY reset signal. PHYRST can also be
(I/O)
(O)
(O)
(O)
(O)
(O)
(O)
(I)
(I)
J H P H Q W 0 R G H
J H P H Q W 0 R G H
RDY/DTACK
RDY/DTACK
J H P H Q W 0 R G H
ADDR[11:0]
DATA[7:0]
WR/RW
WR/RW
RD/DS
RD/DS
SEL
Figure 14 UTOPIA 2 Parallel Interface Read Cycle
t
t
SERS
ADRS
t
RDYRV
t
RDPW
18 of 43
PHY layer and indicates that an interrupt has occurred. The interrupt
must be cleared by the controlling CPU before another interrupt event
can be reported.
in the Management Register Table.
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2 S
2 S
2 S
2 S H H H H U D W L R Q
(MBUS[0:11]), asserting SEL (MGMT1) = "0" and asserting the appro-
priate strobe, which is dependant on the condition of BMODE. The PHY
then drives RDY/DTACK (MGMT[4]) and the Data bus (MDATA[0:7]).
The PHY will de-assert RDY/DTACK to signal the completion of the data
cycle.
(MGMT[2]) = "0", with the WR/RW, (MGMT[3]) = "1". When BMODE =
"0" the data is strobed by setting the WR/RW and RD/DS = "1".
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2 S
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2 S
2 S
the Data (MDATA[0:7]), and asserting the appropriate strobe. The PHY
will drive RDY/DTACK (MGMT[4]) to specify the beginning and end of
the cycle.
and RD/DS (MGMT[2]) = "1". When BMODE = "0" the data is strobed by
setting RD/DS = "1" and setting WR/RW = "0".
PHYINT is an active low interrupt signal. This signal is driven by the
Registers associated with the management interface are described
A read is initiated by the 77V011 driving the Address bus
When BMODE = "1" the data is strobed by asserting RD/DS,
A write is initiated by the 77V011 driving Address bus (MBUS[0:11]),
When BMODE = "1" the data is strobed setting WR/RW (MGMT[3])
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t
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DARV
t
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0 D Q
0 D Q
0 D Q D D D D J H P H
0 D Q
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DARIV
t
SELRH
t
RDYRT
t
ADRH
J H P H Q Q Q Q W 0 R G H
J H P H
J H P H
J H P H Q Q Q Q W 0 R G H : U L W H
J H P H
J H P H
W 0 R G H 5 5 5 5 H D G
W 0 R G H
W 0 R G H : U L W H
W 0 R G H : U L W H
W 0 R G H
W 0 R G H : U L W H
5348drw1
March 15, 2001
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