IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet - Page 15

• Manufacturer Part Number: IDT72V36110
• Description: 128k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
LD
0
0
0
X
1
1
1
WEN
1
1
0
X
1
0
1
REN
Figure 3. Programmable Flag Offset Programming Sequence
0
1
1
1
X
0
1
SEN
1
1
0
1
X
X
X
TM
36-BIT FIFO
WCLK
X
X
X
X
15
RCLK
X
X
X
X
X
Serial shift into registers:
1 bit for each rising WCLK edge
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
32 bits for the 72V36100
34 bits for the 72V36110
Read Memory
No Operation
Write Memory
No Operation
IDT72V36100
IDT72V36110
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
6117 drw06
APRIL 6, 2006