IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet - Page 35

• Manufacturer Part Number: IDT72V36110
• Description: 128k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
D
Q
WCLK
RCLK
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
WCLK
RCLK
WEN
0
REN
0
PAF
WEN
In IDT Standard mode: D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT mode: D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
rising edge of RCLK and the rising edge of WCLK is less than t
REN
SKEW2
- D
- Q
LD
LD
n
n
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
t
CLKL
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
ENS
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
D - (m+1) words in FIFO
t
CLKL
DATA IN OUTPUT REGISTER
t
ENH
t
CLKH
t
CLKH
1
(2)
t
CLK
t
CLK
SKEW2
t
t
ENS
LDS
t
t
CLKL
DS
t
, then the PAF deassertion time may be delayed one extra WCLK cycle.
TM
t
ENS
LDS
t
CLKL
36-BIT FIFO
OFFSET
PAE
2
t
PAFS
35
t
t
t
ENH
DH
LDH
t
t
LDH
t
t
ENH
A
ENS
t
SKEW2
(3)
OFFSET
PAF
PAE OFFSET
t
ENH
D - m words in FIFO
t
t
1
t
DH
ENH
LDH
t
t
ENH
LDH
t
A
COMMERCIAL AND INDUSTRIAL
(2)
TEMPERATURE RANGES
2
PAFS
t
PAFS
PAF OFFSET
). If the time between the
APRIL 6, 2006
D-(m+1) words
in FIFO
6117 drw 23
6117 drw 21
6117 drw 22
(2)