IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet - Page 36

• Manufacturer Part Number: IDT72V36110
• Description: 128k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
WCLK
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
WCLK
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
RCLK
RCLK
WEN
WEN
REN
REN
In IDT Standard Mode: D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT Mode: D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
PAE
WCLK and the rising edge of RCLK is less than t
PAF
SKEW2
t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
CLKH
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
ENS
n words in FIFO
n+1 words in FIFO
t
CLKL
D - (m + 1) words in FIFO
t
ENH
t
(2)
SKEW2
1
,
(3)
t
CLKH
SKEW2
(4)
, then the PAE deassertion may be delayed one extra RCLK cycle.
t
PAES
2
t
ENS
TM
36-BIT FIFO
t
CLKL
36
t
ENS
t
t
ENH
PAFA
n+1 words in FIFO
n+2 words in FIFO
t
ENS
t
ENH
D - m words
in FIFO
(2)
(3)
,
t
PAFA
1
COMMERCIAL AND INDUSTRIAL
PAES
t
PAES
). If the time between the rising edge of
D - (m + 1) words
TEMPERATURE RANGES
2
in FIFO
n words in FIFO
n+1 words in FIFO
APRIL 6, 2006
6117 drw25
6117 drw 24
(2)
,
(3)