IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet - Page 45

• Manufacturer Part Number: IDT72V36110
• Description: 128k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTE:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
1149.1) for the full state diagram.
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the Queue and must be reset after power up of the device. See TRST
description for more details on TAP controller reset.
the normal operation of the IC. The TAP controller state machine is designed
in such a way that, no matter what the initial state of the controller is, the Test-
Logic-Reset state can be entered by holding TMS at high and pulsing TCK five
times. This is the reason why the Test Reset (TRST) pin is optional.
certain instructions are present. For example, if an instruction activates the self
test, then it will be executed when the controller enters this state. The test logic
in the IC is idles otherwise.
Data Path or the Select-IR-Scan state is made.
Instruction Path is made. The Controller can return to the Test-Logic-Reset state
other wise.
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
Run-Test-Idle In this controller state, the test logic in the IC is active only if
Select-DR-Scan This is a controller state where the decision to enter the
Select-IR-Scan This is a controller state where the decision to enter the
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
All state transitions within the TAP controller occur at the rising edge of the
Test-Logic-Reset All test logic is disabled in this controller state enabling
Input = TMS
1
0
Test-Logic
Run-Test/
Reset
Idle
0
Figure 33. TAP Controller State Diagram
1
1
TM
0
36-BIT FIFO
1
Update-DR
Capture-DR
Pause-DR
Exit2-DR
DR-Scan
Exit1-DR
Shift-DR
Select-
45
0
0
0
1
1
1
0
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be “01”.
between TDI and TDO, and the captured pattern gets shifted on each rising edge
of TCK. The instruction available on the TDI pin is also shifted in to the instruction
register.
IR state or Update-IR state is made.
register to be temporarily halted.
IR state or Update-IR state is made.
latched in to the latch bank of the Instruction Register on every falling edge of
TCK. This instruction also becomes the current instruction once it is latched.
registers selected by the current instruction on the rising edge of TCK.
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
Capture-IR In this controller state, the shift register bank in the Instruction
Shift-IR In this controller state, the instruction register gets connected
Exit1-IR This is a controller state where a decision to enter either the Pause-
Pause-IR This state is provided in order to allow the shifting of instruction
Exit2-DR This is a controller state where a decision to enter either the Shift-
Update-IR In this controller state, the instruction in the instruction register is
Capture-DR In this controller state, the data is parallel loaded in to the data
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
0
0
1
1
0
1
1
1
1
1
Capture-IR
Update-IR
Pause-IR
Exit2-IR
IR-Scan
Shift-IR
Exit1-IR
Select-
1
0
0
0
0
6117 drw38
0
0
COMMERCIAL AND INDUSTRIAL
1
TEMPERATURE RANGES
APRIL 6, 2006