IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet - Page 41

• Manufacturer Part Number: IDT72V36110
• Description: 128k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
Word width may be increased simply by connecting together the control
GATE
FIRST WORD FALL THROUGH/
(1)
DATA IN
SERIAL INPUT (FWFT/SI)
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FULL FLAG/INPUT READY (FF/IR)
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
Figure 29. Block Diagram of 65,536 x 72 and 131,072 x 72 Width Expansion
D
0
- Dm
LOAD (LD)
m
#1
72V36100
72V36110
FIFO
IDT
#1
TM
36-BIT FIFO
Dm
m
+1
- Dn
Q
41
n
0
- Qm
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can be
created by ORing OR of every FIFO, and separately ORing IR of every FIFO.
72V36110 devices. D
Q
be attained by adding additional IDT72V36100/72V36110 devices.
0
-Q
Figure 29 demonstrates a width expansion using two IDT72V36100/
72V36100
72V36110
35
FIFO
IDT
#2
from each device form a 72-bit wide output bus. Any word width can
READ CLOCK (RCLK)
n
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
Qm
0
- D
+1
35
- Qn
from each device form a 72-bit wide input bus and
COMMERCIAL AND INDUSTRIAL
m + n
TEMPERATURE RANGES
DATA OUT
6117 drw34
APRIL 6, 2006
GATE
(1)