IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet - Page 17

• Manufacturer Part Number: IDT72V36110
• Description: 128k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q8
D/Q8
D/Q8
16
16
8
8
IDT72V36100 ⎯
EMPTY OFFSET REGISTER (PAE)
EMPTY OFFSET REGISTER (PAE)
FULL OFFSET REGISTER (PAF)
FULL OFFSET REGISTER (PAF)
15
15
7
7
14
14
6
6
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
13
13
5
5
x9 Bus Width
12
12
4
4
11
11
3
3
10
10
2
2
TM
D/Q0
D/Q0
D/Q0
36-BIT FIFO
D/Q0
1
1
9
9
17
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
6th Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
5th Parallel Offset Write/Read Cycle
D/Q8
D/Q8
D/Q8
D/Q8
D/Q8
D/Q8
16
16
8
8
IDT72V36110 ⎯
EMPTY OFFSET REGISTER (PAE)
EMPTY OFFSET REGISTER (PAE)
EMPTY OFFSET REGISTER (PAE)
FULL OFFSET REGISTER (PAF)
FULL OFFSET REGISTER (PAF)
FULL OFFSET REGISTER (PAF)
15
15
7
7
14
14
6
6
13
13
5
5
COMMERCIAL AND INDUSTRIAL
# of Bits Used:
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
x9 Bus Width
12
12
4
4
TEMPERATURE RANGES
11
11
3
3
10
10
2
2
APRIL 6, 2006
6117 drw07a
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
D/Q0
17
17
1
1
9
9