IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet - Page 19

• Manufacturer Part Number: IDT72V36110
• Description: 128k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

setup by setting OR HIGH. During this period, the internal read pointer is set
to the first location of the RAM array.
contents of the first location appear on the outputs. Since FWFT mode is selected,
the first word appears on the outputs, no LOW on REN is necessary. Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for the relevant timing
diagram.
and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit
When OR goes LOW, Retransmit setup is complete; at the same time, the
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
TM
36-BIT FIFO
19
synchronized to RCLK, thus on the second rising edge of RCLK after RT is setup,
the PAE flag will be updated. HF is asynchronous, thus the rising edge of RCLK
that RT is setup will update HF. PAF is synchronized to WCLK, thus the second
rising edge of WCLK that occurs t
is setup will update PAF. RT is synchronized to RCLK.
“normal latency” or “zero latency”. Figure 11 and Figure 12 mentioned
previously, relate to “normal latency”. Figure 13 and Figure 14 show “zero
latency” retransmit operation. Zero latency basically means that the first data
word to be retransmitted, is placed onto the output register with respect to the
RCLK pulse that initiated the retransmit.
The Retransmit function has the option of two modes of operation, either
SKEW
after the rising edge of RCLK that RT
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
APRIL 6, 2006