IDT72V36110 Integrated Device Technology, IDT72V36110 Datasheet - Page 43

• Manufacturer Part Number: IDT72V36110
• Description: 128k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

TRST
NOTE:
1. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
SYSTEM INTERFACE PARAMETERS
NOTE:
1. 50pf loading on external output signals.
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
Data Output Hold
Data Output
Parameter
TDI/
TMS
TDO
TCK
Data Input
(1)
t
JTCKF
Symbol
t
t
DOH
t
DO
t
t
DS
DH
JRST
(1)
(1)
Test Conditions
t
JTCKL
t
t
rise=3ns
fall=3ns
t
t
JTCKR
JRSR
t
t
TCK
DS
Min.
10
10
0
-
t
DH
IDT72V36100
IDT72V36110
Figure 31. Standard JTAG Timing
t
JTCKH
Max. Units
20
TM
-
-
-
36-BIT FIFO
ns
ns
ns
43
(V
NOTE:
1. Guaranteed by design.
JTAG AC ELECTRICAL
CHARACTERISTICS
JTAG Clock Input Period t
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
JTAG Reset Recovery
CC
= 3.3V
Parameter
±
5%; Tcase = 0°C to +85°C)
Symbol
t
t
t
t
t
t
TCK
JTCKH
JTCKL
JTCKR
JTCKF
JRST
JRSR
COMMERCIAL AND INDUSTRIAL
Conditions Min. Max. Units
Test
t
DO
-
-
-
-
-
-
-
TEMPERATURE RANGES
100
40
40
50
50
-
-
APRIL 6, 2006
TDO
5
5
-
-
-
-
-
(1)
(1)
6117 drw36
ns
ns
ns
ns
ns
ns
ns