HT46R71D-1 Holtek Semiconductor, HT46R71D-1 Datasheet
HT46R71D-1
Related parts for HT46R71D-1
HT46R71D-1 Summary of contents
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... Watchdog Timer with regulator power Buzzer output Internal 12kHz RC oscillator General Description The HT46R71D 8-bit high performance, RISC architecture microcontroller device specifically de- signed for A/D with LCD applications that interface di- rectly to analog signals, such as those from sensors. The advantages of low power consumption, I/O flexibil- ity, timer functions, oscillator options, Dual slope A/D Rev ...
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... Block Diagram Rev. 1.00 HT46R71D-1 2 May 14, 2007 ...
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... Duty COM0~COM2 are the common outputs for the LCD panel plate. Segment LCD driver outputs for the LCD panel segments. Output Bandgap voltage output pin. (for internal use) Regulator output 3.3V Charge pump output (a capacitor is required to be connected) Charge pump capacitor, positive Charge pump capacitor, negative 3 HT46R71D-1 Description May 14, 2007 ...
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... No load, ADC on =4MHz, SYS ADCCLK=125kHz 3V No load, system HALT, LCD off at HALT load, system HALT, LCD off at HALT, ADC off load, system HALT, LCD off at HALT, ADC off 5V 4 HT46R71D-1 Description Ta=25 C Min. Typ. Max. Unit 2.2 5 0.8 1 ...
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... Charge pump on 2.2 Charge pump off 3.7 No load 3 V =3.7V~5.5V DD Charge pump off Current 10mA V =2.4V~3.6V DD Charge pump on Current 6mA @3.3V 1.45 @3.3V Amplifier, no load 0.2 Integrator, no load 1 5 HT46R71D-1 Typ. Max. Unit 0. 0. ...
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... Interrupt Pulse Width INT Note 1/f SYS SYS Rev. 1.00 Test Conditions Min. V Conditions DD 2.2V~5.5V 400 3V 5V 2.2V~5. Power-up or wake-up from HALT 0. HT46R71D-1 Ta=25 C Typ. Max. Unit 4000 kHz 12 kHz 15 kHz 4000 kHz 90 180 s 65 130 1024 SYS May 14, 2007 ...
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... Program Counter S10 Program Counter S10~S0: Stack register bits @7~@0: PCL bits 7 HT46R71D ...
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... Table Location * P10 Table Location P10~P8: Current program counter bits 8 HT46R71D May 14, 2007 * ...
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... MP0 and MP1. RAM Mapping Rev. 1.00 HT46R71D-1 Bank 1 contains the LCD Data Memory locations. After first setting the value of 01H to access Bank 1 this bank must then be accessed indirectly using the Memory Pointer MP1. With BP set to a value of 01H , ...
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... Internal Timer/Event Counter 1 request flag (1=active; 0=inactive) For test mode used only. Must be written otherwise may result in unpredictable operation. INTC 0 (0BH) Register Controls the ADC interrupt (1=enabled; 0:disabled) Unused bit, read as 0 ADC request flag (1=active; 0=inactive) INTC 1 (1EH) Register 10 HT46R71D-1 Function Function May 14, 2007 ...
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... To return from the interrupt subroutine, RET or RETI may be invoked. RETI sets the EMI bit and en- ables an interrupt service, but RET does not. Rev. 1.00 HT46R71D-1 Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses are serviced on the latter of the two T2 pulses if the corresponding interrupts are enabled ...
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... WDT OSC enable strongly recommend use to use 10 for WDT OSC enable Reserved WDTC (1CH) Register Function The WDT counter data value. This register is read only used for temperature adjusting. WDTD (1DH) Register 12 HT46R71D division ration range. May 14, 2007 ...
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... PAC Register PA data Register PAC.1 PA PA0/PA1 Pin Function Control 13 HT46R71D-1 CLR WDT1 and CLR WDT2 . CLR WDT times selection option. PA data Register Output Function PA.1 X PA0=0, PA1=0 X PA0=BZ, PA1=BZ X PA0=0, PA1=Input X PA0=BZ, PA1=Input X PA0=Input, PA1=0 X PA0=Input, PA1=Input ...
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... PDF flag is cleared by system power- executing the CLR WDT instruction, and is set by executing the HALT instruction. On the other hand, the TO flag is set if WDT time-out occurs, and causes a wake-up that only re- sets the program counter and SP, and leaves the others in their original state. 14 HT46R71D-1 May 14, 2007 ...
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... Prescaler, Divider WDT Timer/Event Counter Input/output Ports Stack Pointer (system SYS Note: RESET Conditions 15 HT46R71D-1 000H Disabled Cleared Cleared. After master reset, WDT starts counting Off Input mode Points to the top of the stack Reset Circuit * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference ...
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... HT46R71D-1 RES Reset WDT Time-out (HALT) (HALT)* 1uuu uuuu 1uuu uuuu 1uuu uuuu 1uuu uuuu ---- ---0 ---- ---u uuuu uuuu uuuu uuuu 0000H 0000H ...
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... Therefore, only a 1-cycle measurement can be made until the T0ON/T1ON bit is again set. The cycle measurement will re-function as long as it receives further transient pulses. In this operation mode, the timer/event counter Timer/Event Counter 0 Timer/Event Counter 1 17 HT46R71D-1 May 14, 2007 ...
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... Defines the TMR1 internal clock source (0=f Defines the operating mode T1M1, T1M0= 01=Event count mode (External clock) 10=Timer mode (Internal clock) 11=Pulse Width measurement mode (External clock) 00=Unused TMR1C (11H) Register 18 HT46R71D-1 ; 1=Int.RCOSC (Internal RC OSC)) SYS /4; 1=Int.RCOSC (Internal RC OSC)) SYS May 14, 2007 ...
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... CMOS outputs or Schmitt trigger inputs with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an in- Rev. 1.00 HT46R71D-1 put, the corresponding latch of the control register must write 1 . The input source also depends on the control register. If the control register bit the input will read the pad state ...
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... The CHPCKD4~CHPCKD0 bits are use to set the clock divider to generate the desired clock frequency for proper charge pump operation. The actual frequency is determined by the following formula. Actual Charge Pump Clock HT46R71D FIL /16)/(CHPCKD +1). SYS May 14, 2007 ...
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... The ADCD register is the A/D Chopper clock divider register, which defines the chopper clock to the ADC module. 21 HT46R71D-1 Function OPA Description ADC The whole module is disable, ...
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... The ADCMPO bit is read only for the comparator output, while the ADINTM bits can set the ADCMPO trigger mode for interrupt generation. Rev. 1.00 HT46R71D-1 The following descriptions are based the fact that ADRR0=0 The amplifier and buffer combination, form a differential input pre-amplifier which amplifies the sensor input sig- nal ...
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... ADCD register) ADC resisters selection (4/6 VOREG, 1/6 VOREG) INT CMP (4.4/6 VOREG, 1/6 VOREG) INT CMP ADCR (18H) Register 23 HT46R71D (1/3) VDSO (2 Tc/Ti). A (Based on ADRR0=0) and C to determine the Ti value, to allow DS DS value to operate between 5/6VDSO and C May 14, 2007 ...
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... LCD Driver Output The output structure of the device LCD driver can be either selectable via configuration option (i.e., 1/2 duty or 1/3 duty). The bias type LCD driver is R type only. The LCD driver bias voltage can be 1/2 bias or 1/3 bias by option. 24 HT46R71D-1 Display Memory May 14, 2007 ...
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... Unused bit, read as unknown In HALT mode, IRC clock enable or disable selection bit. 0: IRC clock enable and Int.RCOSC on. 1: IRC clock disabled. LVD enable/disable (1/0) LVD detection output (1/0) 1: low voltage detected, read only. 0: low voltage not detected. MODE (09H) Register 25 HT46R71D-1 May 14, 2007 ...
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... Low Voltage Reset Ext. WDT RC Oscillator Off Enabled Off 1 Disabled Off 26 HT46R71D-1 IRC Clock System Clock Mode External Enabled Normal RC Oscillator Enabled and Int. Off Idle RCOSC ON Disabled and Int. Off HALT RCOSC ON Disabled and Int. ...
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... INT trigger edge selection: disable; high to low; low to high; low to high or high to low Partial-lock selection: Page0~3, Page4~6, Page7. Rev. 1.00 Options /4 SYS means the configuration option se HT46R71D May 14, 2007 ...
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... Note: The resistance and capacitance value for the reset circuit should be designed in such a way as to ensure that V is stable and remains within a valid operating voltage range before bringing RES high Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.00 HT46R71D-1 28 May 14, 2007 ...
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... Within the Holtek microcontroller instruction set are a range of add and Rev. 1.00 HT46R71D-1 subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en- sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 30 HT46R71D-1 Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 31 HT46R71D-1 Cycles Flag Affected 1 None Note 1 ...
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... Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. [m] ACC AND [ HT46R71D-1 May 14, 2007 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF 33 HT46R71D-1 May 14, 2007 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared PDF 1 TO, PDF 34 HT46R71D-1 May 14, 2007 ...
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... None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. ACC ACC OR [ HT46R71D-1 May 14, 2007 ...
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... Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. ACC.(i+1) [m]. 0~6) ACC.0 [m].7 None 36 HT46R71D-1 May 14, 2007 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1 0~6) ACC [m]. HT46R71D-1 May 14, 2007 ...
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... ACC [m] 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None 38 HT46R71D-1 May 14, 2007 ...
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... The immediate data specified by the code is subtracted from the contents of the Accumu- lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC x OV HT46R71D-1 May 14, 2007 ...
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... Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None 40 HT46R71D-1 May 14, 2007 ...
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... Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op- eration. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR HT46R71D-1 May 14, 2007 ...
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... Package Information 48-pin SSOP (300mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 395 291 8 613 HT46R71D-1 Max. 420 299 12 637 May 14, 2007 ...
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... Product Tape and Reel Specifications Reel Dimensions SSOP 48W Symbol A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Description 43 HT46R71D-1 Dimensions in mm 330 1 100 0.1 13+0.5 0.2 2 0.5 32.2+0.3 0.2 38.2 0.2 May 14, 2007 ...
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... Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Description 44 HT46R71D-1 Dimensions 0.3 16 0.1 1.75 0.1 14.2 0.1 2 Min. 1.5+0.25 4 0.1 2 0.1 12 0.1 16.2 0.1 2.4 0.1 3.2 0.1 0.35 0.05 25.5 May 14, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 HT46R71D-1 45 May 14, 2007 ...